Custom Designed Integrated Circuits / Introduction to Embedded Systems




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Custom Designed Integrated Circuits /
Introduction to Embedded Systems

ProjeCtS 2002:HT1


VGA Controller
and
PS2-mouse port

Lab engineer: Björn Lundblad


Examiner: Alf Johansson

Date: 2016-04-27


Issue: 1.4


Contents

1 Purpose 3

2 The project 3

3 Reports 3

4 Project "VGA Controller" 4

4.1 Description 4

4.2 Specification 5

4.3 Block diagram, VGA Controller 5

4.4 VGA Interface 7

4.5 Sprite control 7

4.6 Graphic Memory (RAM) / Sprites 7

4.7 Timing control 8

4.7.1 VGA monitor timing 640*480 mode 8

4.8 Analogue video signals 9

5 Test hardware 10

5.1 Description 10

5.2 -Controller interface 10

5.3 Program sequences 11

5.4 Software (Master students only) 12

5.5 Appendix A 13

5.6 Appendix B 14



Revision history

      1. 1.0 Original issue

      2. 1.2 Errors corrected. UART Test board added for VGA tests.

2002-09-26 1.3 Mouse CPU interface added.

2002-10-05 1.4 PS2 mouse interface replaces mouse interface



1Purpose


The goal of the project is to:

  • use VHDL to design a circuit that shall be implemented in a FPGA.

  • use VHDL to create a structured design.

  • use FSM (State machine) description for sequence nets.

  • use a test bench and simulator to verify the design.

  • use synthesis and FPGA-tools to realize (implement)the design.



2The project


The project consists of several steps:

  • Design one of the proposed circuits (UART, Video Signal Controller).

  • Design a test bench in VHDL for input signals.

  • Verify the design with a simulator and test bench

  • Show the test bench simulations to the supervisor (lab engineer or lecturer).

  • Synthesise the design.

  • Verify the design in hardware and show the lab engineer/lecturer the result.

  • Write a project report.



3Reports


The test bench shall be presented and the design in FPGA tested and presented before the report is handed over to the teacher.

The report must include:

Front page.

A description of the design in graphical form: block diagrams, state machine graphs etc.

Test bench described in VHDL

Report from synthesis (Leonardo).



4Project "VGA Controller"

4.1Description


The VGA-controller shall control a PC-monitor (VGA-monitor). The monitor shall have synchronisation pulses and video signals. A H-synch-pulse (horizontal) will restart a sweep of a horizontal line from left to right. A V-sync-pulse will restart a new frame and the next horizontal line will start at the upper left corner of the screen. The timing of the sync-pulses is defined for a number of VGA-modes. In this project a 640*480 mode shall be used. These means that there are 640 visible picture points (pixels) per line and 480 visible lines. The frame update frequency is 60Hz. The monitor shall have three analogue colour signals (video). These signals represent the colours red, green and blue. We chose to have only different 4 analogue values for each colour and totally 64 different colours. In order to save the pixel memory only a small part of the picture is stored ( a cursor sprite). This sprite can be positioned anywhere on the screen. The background pattern is stored in another sprite (background sprite).

There shall (this is an option and not mandatory) be a possibility to connect a modified PC-mouse to position the cursor sprite on the screen. As an alternative use a simple Controller interface to control the cursor sprite.






4.2Specification


The VGA entity specification is shown below. The connection to the VGA monitor is through three analogue colour signals (RGB) and two synchronisation signals (h-sync and v-sync). The input clk (system clock) shall have frequency as the internal pixel-clock. The vga entity also has an interface to a micro controller (PIC16F628). Cursor position registers can be written and a status bit can be read. The PC-mouse sends two signals per move direction (mouse1_0/1 and moues2_0/1).

entity vga is

port( clk, reset, wr, rd,a0,a1,a2: in std_logic;

dbus: inout std_logic_vector(3 downto 0);

int: out std_logic;

tx0, rx1: in std_logic;

rx0, tx1: out std_logic;

video: out std_logic_vector(5 downto 0);

h_sync, v_sync: out std_logic;

ps2_data: inout std_logic;

ps2_clk: out std_logic

);


end;

4.3 Block diagram, VGA Controller



HSync

Timing control



clk



VSync



reset

Blanking





X(9 downto 0)



Y(9 downto 0)

Sprite
control

Background sprite

Xbs(2 downto 0)

6


DA

Ybs(2 downto 0)



3 VGA



Cursor sprite

Xcs(2 downto 0)

C interface



Ycs(2 downto 0)





mouseX, mouseY



PS2 mouse interface





ps2_data

ps2_clk

4.4 VGA Interface


Pin

VGA-signal

Description

Signal level

1

RED

Video colour signal, red

Analogue 0-0.7V

2

GREEN

Video colour signal, green

Analogue 0-0.7V

3

BLUE

Video colour signal, blue

Analogue 0-0.7V

4

ID2

Not used (open)




5

Ground







6

Ground

Red-return




7

Ground

Green-return




8

Ground

Blue-return




9

Key, no pin







10

Ground

Sync-return




11

ID0

Not used (open)




12

ID1

Not used (open)




13

HSYNC

Horizontal Synchronisation, positive logic

TTL 5V

14

VSYNC

Vertical Synchronisation, positive logic

TTL 5V

15

Reserved






4.5 Sprite control


The Sprite control block compares the X,Y-counters to the cursor position (Xc,Yc) and swithes between background sprite and cursor sprite. Several methods can be used when designing this block. Direct comparison of address ranges will require both comparators and adders. This may require to many CLBs . A more effective design with state machines in the Cursor control block and only equal comparators in the Sprite control block.

4.6 Graphic Memory (RAM) / Sprites


Normally the graphic memory shall have one memory position (16 bit or 32 bits for each position) for each pixel. In VGA-mode (640*480) this requires a memory size of 600kB for 16 bit colour resolution. In our case where we only use 6 bit colours it still requires 300 kB. This is not possible to implement as internal “distributed RAM” (see lecture notes). With the limited memory available we choose to only show a small (8 pixels*8 pixels) picture area (a sprite) to show a cursor. This sprite can be position anywhere on the screen. The contents of the sprite is fixed (ROM) or modifiable (RAM). Such a sprite requires 12 CLBs ( 8*8*6/32). A 16*16 (6 bit colour) sprite accordingly requires 48 CLBs. The same number of CLBs are required for both ROM and RAM. There are 196 CLBs in the circuit that shall be used (XCS10). The background pattern shall be stored in a 8*8 sprite. The ROM (or RAM) shall be written in VHDL (inferred ROM/RAM).

4.7 Timing control


The Timing control block is responsible for X- and Y-counters and for generation of sync-signals (h-sync, v-sync). It’s suitable to do this block as a state machine.

4.7.1VGA monitor timing 640*480 mode


Frame frequency: 60 pictures/s => 16784 s/frame

Horizontal frequency: 31,47 kHz

Horizontal lines (displayed): 480

Time per line: 31,80 (nominal 31.78) s

Frame display time: 480*31,77=15250 s

Frame retrace time: 16784-15250=1534 s

Frame retrace lines: 1534/31,77=48 lines

Horizontal lines (total) 480+48=528

Horizontal display time: 503T (25,17 s)

Number of pixels /line(displayed): 503

Number of pixels/line (total): 636

Horizontal blanking: 133T (31,77-25,17= 6,6 s)

Pixel frequency: 1/(25,17/503) MHz = 20,0 (19,984) MHz

Pixel time T: 50 ns

Sync pulse (H-sync): 19T



4.8Analogue video signals


Each colour (RGB) is digitally represented by 2 bits (red(0) and red(1) etc). The monitor shall have an analogue input signal. Therefore a simple DA (Digital to Analogue) converter is connected to each colour output from the FPGA. See figure.


5Test hardware

5.1Description


To test the FPGA design a special PCB is designed. The board has a Xilinx Spartan XCS10 circuit and a micro controller PIC16F628. The board also has drivers for RS232 (Max 202) and a power supply regulator. There are two adaptors on the board, for VGA connection and for PS2 mouse connection.

Programming of the FPGA is done in slave-serial mode.

The board shall be supplied with 8-12V DC. See drawing diagram for details.

5.2 -Controller interface


The C is programmed with small program that moves the cursor in a special pattern. It’s possible for the students to write their own -controller programs.

a2

a1

a0

(wr=’1’, rd=’0’)

(wr=’0’,rd=’1’)

0

0

0

CursorX(3 downto 0) <=dbus

dbus<=”000” & ”vertical blanking”;

0

0

1

CursorX(7 downto 4) <= dbus




0

1

0

CursorX(9 downto 8) <= dbus( 1 downto 0)




0

1

1

CursorY(3 downto 0) <=dbus




1

0

0

CursorY(7 downto 4) <= dbus




1

0

1

CursorY(9 downto 8) <= dbus(1 downto 0)




1

1

0

ps2_register

NA

1

1

1

ps2_data

ps2_data

The data bus between the Controller and the FPGA is only four bits wide ( a nibble) so a 12 bit wide register must be written three times.

The PIC16-processor uses port A as a bi-directional data bus and port B for control signals. All handling of the data bus and control signals is controlled by the software in the PIC-processor. The micro controller and the FPGA circuit use the same clock signal, which is generated by a crystal oscillator at 20 MHz.

.

5.3Program sequences


As all signals from the PIC-processor are generated by software the timing requirements are not hard. A typical sequence when data is written to the UART transmit register is shown below. The timing can’t be faster than shown.










5.4 Software (Master students only)


The test software writes three 4 bit register for X position and three 4 bit registers for Y position. This writing of the registers must be done during vertical blanking signal. Therefore the vertical blanking signal is accessible by reading status register (bit 0).

Minimum level:

Write a C-program for the PIC16F628 that moves the cursor on the screen in a predefined pattern



Optional:

Write a C-program that can communicate with the PS2-mouse device. The HW shall be added with a component that is the interface to the PC-mouse.



5.5 Appendix A


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;
entity cur_sprite is

port(spx, spy: in std_logic_vector(2 downto 0);

sp_rgb: out std_logic_vector(5 downto 0));

end;
architecture rtl of cur_sprite is

type rom_table is array(0 to 63) of std_logic_vector(5 downto 0);

signal rom: rom_table :=

("000000","000000","111111","111111", -- row 1

"111111","111111","111111","111111", -- row 1

"000000","000000","000000","000000", -- row 2

"111111","111111","111111","111111", -- row 2

"000000","000000","000000","000000", -- row 3

"111111","111111","111111","111111", -- row 3

"000000","000000","111111","111111", -- row 4

"111111","111111","111111","111111", -- row 4

"000000","000000","111111","111111", -- row 5

"111111","000000","000000","111111", -- row 5

"000000","111111","111111","111111", -- row 6

"000000","000000","000000","111111", -- row 6

"111111","111111","111111","000000", -- row 7

"000000","000000","000000","000000", -- row 7

"111111","111111","000000","000000", -- row 8

"000000","000000","000000","000000");-- row 8


begin

sp_rgb<=rom(conv_integer(spy & spx));



end;

5.6 Appendix B


Connection pins for FPGA and external connectors. The following connection table shall be used if the board version-2001 is used.

Port signal

Description

FPGA pin #

Connector

clk

Main clock 20 MHz

13

NA

reset

Active high asynchronous reset. From C to FPGA

5

NA

wr

synchronous write signal

18

NA

rd

asynchronous read

19

NA

a0

address bit 0

24

NA

a1

address bit 1

23

NA

a2

address bit 2

20




dbus(0)

bi-directional data bus

9

NA

dbus(1)

bi-directional data bus

8

NA

dbus(2)

bi-directional data bus

7

NA

dbus(3)

bi-directional data bus

6

NA













Red(0)

Video colour red bit 0

47

P3:7

Red(1)

Video colour red bit 1

48

P3:8

Green(0)

Video colour green bit 0

46

P3:5

Green(1)

Video colour green bit 1

49

P3:6

Blue(0)

Video colour blue bit 0

45

P3:3

Blue(1)

Video colour blue bit 1

50

P3:4

H_sync

Horizontal sync pulse for VGA monitor

40

P3:2

V_sync

Vertical sync pulse for VGA monitor

44

P3:1













ps2_data

PS2 mouse interface, bidirectional data

65




ps2_clk

PS2 mouse interface, bidirectional clock

66






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