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Laboratory Manual to the Course Microprocessors (CENG 329)

EXPERIMENT 1




ÇANKAYA UNIVERSITY

COMPUTER ENGINEERING DEPARTMENT




EXPERIMENT 1

GETTING STARTED WITH THE Z8 Encore! PROCESSOR




OBJECTIVE


These tutorials assume no previous experience of assembly language programming or digital signal processing (DSP). However, some basic knowledge of high-level programming is assumed because several of the examples use C code. Some basic electronics knowledge would also be useful for connecting external components to the DSK.

As far as using the High Performance 8-Bit Microcontrollers Z8 Encore!® 64K Series is concerned, it is assumed that the hardware and software have been successfully installed and that the user understands the basic operation e.g. how to load the sample program, single-step it and run it, how to read the CPU registers etc.


1. THEORY

The Z8 Encore!® MCU family of products are a line of ZiLOG microcontroller products based upon the 8-bit eZ8 CPU. The Z8 Encore!® 64K Series, hereafter referred to collectively as the Z8 Encore!® or the 64K Series adds Flash memory to ZiLOG’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The Z8 Encore!® 64K Series also includes ROM devices that are pin- and function-compatible with the Flash products. The ROM devices provide a low-cost alternative for customers who do not require the reprogrammability of the Flash devices. The new eZ8 CPU is upward compatible with existing Z8® instructions. The rich peripheral set of the Z8 Encore!® makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors.


1.1. FEATURES


• 20MHz eZ8 CPU

• Up to 64KB Flash (or optional ROM) with in-circuit programming capability (Flash only)

• Up to 4KB register RAM

• 12-channel, 10-bit analog-to-digital converter (ADC)

• Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control

• I2C *

• Serial Peripheral Interface

• Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders

• Up to four 16-bit timers with capture, compare, and PWM capability

• Watch-Dog Timer (WDT) with internal RC oscillator

• 3-channel DMA

• Up to 60 I/O pins

• 24 interrupts with configurable priority

• On-Chip Debugger

• Voltage Brown-out Protection (VBO)

• Power-On Reset (POR)

• 3.0-3.6V operating voltage with 5V-tolerant inputs

• 0° to +70°C and -40° to +105°C operating temperature ranges


* The Inter-Integrated Circuit, (pronounced I-squared-C) is a serial computer bus invented by Philips. It is used to connect low-speed peripherals in an embedded system or motherboard.

Figure 1 illustrates the block diagram of the architecture of the Z8 Encore!® 64K Series.




Figure 1. Z8 Encore!® 64K Series Block Diagram

1.1.1. CPU and Peripheral Overview eZ8 CPU Features


The eZ8, ZiLOG’s latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include:

• Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory

• Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks

• Compatible with existing Z8® code

• Expanded internal Register File allows access of up to 4KB

• New instructions improve execution efficiency for code developed using higher-level programming languages, including C

• Pipelined instruction fetch and execution

• New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL

• New instructions support 12-bit linear addressing of the Register File

• Up to 10 MIPS operation

• C-Compiler friendly

• 2-9 clock cycles per instruction

For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual available for download at www.zilog.com.

1.1.2. General Purpose I/O

The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for general purpose I/O (GPIO). Each pin is individually programmable.
1.1.3. Flash Controller

The Flash Controller programs and erases the Flash memory.

10-Bit Analog-to-Digital Converter

The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from up to 12 different analog input sources.


1.1.4. UARTs

Each UART is full-duplex and capable of handling asynchronous data transfers. The UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.

1.1.5. I2C

The inter-integrated circuit (I2C®) controller makes the Z8 Encore!® compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line.


1.1.6. Serial Peripheral Interface


The serial peripheral interface (SPI) allows the Z8 Encore!® to exchange data between other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.

1.1.7. Timers


Up to four 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages.

1.1.8. Interrupt Controller


The 64K Series products support up to 24 interrupts. These interrupts consist of 12 internal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable interrupt priority.

1.1.9. Reset Controller


The Product Specification® can be reset using the RESET pin, power-on reset, Watch-Dog Timer (WDT), STOP mode exit, or Voltage Brown-Out (VBO) warning signal.

1.1.10. On-Chip Debugger

The Z8 Encore!® features an integrated On-Chip Debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming the Flash, setting breakpoints and executing code. A single-pin interface provides communication to the OCD.


1.1.11. DMA Controller


The 64K Series features three channels of DMA. Two of the channels are for register RAM to and from I/O operations. The third channel automatically controls the transfer of data from the ADC to the memory.
1.2. eZ8 CPU INSTRUCTION SET. ASSEMBLY LANGUAGE PROGRAMMING INTRODUCTION

The eZ8 CPU assembly language provides a means for writing an application program without having to be concerned with actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values.

Each assembly language program consists of a series of symbolic commands called statements. Each statement can contain labels, operations, operands and comments.

Labels can be assigned to a particular instruction step in a source program. The label identifies that step in the program as an entry point for use by other instructions.

The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process.

The source program is processed (assembled) by the assembler to obtain a machine language program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example.


Assembly Language Source Program Example


JP START ; Everything after the semicolon is a comment.

START: ; A label called “START”. The first instruction (JP START) in this

; example causes program execution to jump to the point within the

; program where the START label occurs.

LD R4, R7 ; A Load (LD) instruction with two operands. The first operand,

; Working Register R4, is the destination. The second operand,

; Working Register R7, is the source. The contents of R7 is written into R4.

LD 234H, #%01 ; Another Load (LD) instruction with two operands.

; The first operand, Extended Mode Register Address 234H,

; identifies the destination. The second operand, Immediate Data

; value 01H, is the source. The value 01H is written into the

; Register at address 234H.



1.2.1. Assembly Language Syntax


For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ’source, destination’, but ordering is opcode-dependent. The following instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler.

Example 1: If the contents of Registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is:

Assembly Language Syntax Example 1

Assembly Language Code ADD 43H, 08H (ADD dst, src)

Object Code 04 08 43 (OPC src, dst)

Example 2: In general, when an instruction format requires an 8-bit register address, that address can specify any register location in the range 0 - 255 or, using Escaped Mode Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H, the assembly syntax and resulting object code is:

Assembly Language Syntax Example 2

Assembly Language Code ADD 43H, R8 (ADD dst, src)

Object Code 04 E8 43 (OPC src, dst)
See the device-specific Product Specification to determine the exact register file range available. The register file size varies, depending on the device type.
1.2.2. eZ8 CPU Instruction Notation

In the eZ8 CPU Instruction Summary and Description sections, the operands, condition codes, status flags, and address modes are represented by notational shorthand that is described in Table 1.


Table 1. Notational Shorthand

Notation Description Operand Range


b Bit b b represents a value from 0 to 7

(000B to 111B).

cc Condition Code — See Condition Codes overview in

Table 1. Notational Shorthand (Continued)

Notation Description Operand Range


the eZ8 CPU User Manual.

DA Direct Address Addrs Addrs. represents a number in the

range of 0000H to FFFFH

ER Extended Addressing Register Reg Reg. represents a number in the

range of 000H to FFFH

IM Immediate Data #Data Data is a number between 00H to

FFH

Ir Indirect Working Register @Rn n = 0 –15



IR Indirect Register @Reg Reg. represents a number in the

range of 00H to FFH

Irr Indirect Working Register Pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14

IRR Indirect Register Pair @Reg Reg. represents an even number in

the range 00H to FEH

p Polarity p Polarity is a single bit binary value

of either 0B or 1B.

r Working Register Rn n = 0 – 15

R Register Reg Reg. represents a number in the

range of 00H to FFH

RA Relative Address X X represents an index in the range of

+127 to –128 which is an offset

relative to the address of the next instruction

rr Working Register Pair RRp p = 0, 2, 4, 6, 8, 10, 12, or 14

RR Register Pair Reg Reg. represents an even number in

the range of 00H to FEH

Vector Vector Address Vector Vector represents a number in the

range of 00H to FFH

X Indexed #Index The register or register pair to be

indexed is offset by the signed

Index value (#Index) in a +127 to

– 128 range.


Table 2 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections.
Table 2. Additional Symbols

Symbol Definition


dst Destination Operand

src Source Operand

@ Indirect Address Prefix

SP Stack Pointer

PC Program Counter

FLAGS Flags Register

RP Register Pointer

# Immediate Operand Prefix

B Binary Number Suffix

% Hexadecimal Number Prefix

H Hexadecimal Number Suffix
An arrow indicates assignment of a value. For example,

dst  dst + src

indicates the source data is added to the destination data and the result is stored in the destination location.

1.2.3. Condition Codes


The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc) instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which forms Bits 7:4 of the conditional jump instructions. The condition codes are summarized in Table 3. Some binary condition codes can be created using more than one assembly code mnemonic. The result of the flag test operation decides if the conditional jump is executed.

Table 3. Condition Codes


Assembly

Binary Hex Mnemonic Definition Flag Test Operation

0000 0 F Always False –

0001 1 LT Less Than (S XOR V) = 1

0010 2 LE Less Than or Equal (Z OR (S XOR V)) = 1

0011 3 ULE Unsigned Less Than or Equal (C OR Z) = 1

0100 4 OV Overflow V = 1

0101 5 Ml Minus S = 1

0110 6 Z Zero Z = 1

0110 6 EQ Equal Z = 1

0111 7 C Carry C = 1

0111 7 ULT Unsigned Less Than C = 1

1000 8 T (or blank) Always True –

1001 9 GE Greater Than or Equal (S XOR V) = 0

1010 A GT Greater Than (Z OR (S XOR V)) = 0

1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0) = 1

1100 C NOV No Overflow V = 0

1101 D PL Plus S = 0

1110 E NZ Non-Zero Z = 0

1110 E NE Not Equal Z = 0

1111 F NC No Carry C = 0

1111 F UGE Unsigned Greater Than or Equal C = 0
1.2.4. eZ8 CPU Instruction Classes

eZ8 CPU instructions can be divided functionally into the following groups:

• Arithmetic

• Bit Manipulation

• Block Transfer

• CPU Control

• Load

• Logical



• Program Control

• Rotate and Shift

Tables 4 through 11 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instructions can be considered as a subset of more than one category. Within these tables, the source operand is identified as ’src’, the destination operand is ’dst’ and a condition code is ’cc’.

Table 4. Arithmetic Instructions

Mnemonic Operands Instruction

ADC dst, src Add with Carry

ADCX dst, src Add with Carry using Extended Addressing

ADD dst, src Add

ADDX dst, src Add using Extended Addressing

CP dst, src Compare

CPC dst, src Compare with Carry

CPCX dst, src Compare with Carry using Extended Addressing

CPX dst, src Compare using Extended Addressing

DA dst Decimal Adjust

DEC dst Decrement

DECW dst Decrement Word

INC dst Increment

INCW dst Increment Word

MULT dst Multiply

SBC dst, src Subtract with Carry

SBCX dst, src Subtract with Carry using Extended Addressing

SUB dst, src Subtract

SUBX dst, src Subtract using Extended Addressing

Table 5. Bit Manipulation Instructions

Mnemonic Operands Instruction


BCLR bit, dst Bit Clear

BIT p, bit, dst Bit Set or Clear

BSET bit, dst Bit Set

BSWAP dst Bit Swap

CCF — Complement Carry Flag

RCF — Reset Carry Flag

SCF — Set Carry Flag

TCM dst, src Test Complement Under Mask

TCMX dst, src Test Complement Under Mask using Extended Addressing

TM dst, src Test Under Mask

TMX dst, src Test Under Mask using Extended Addressing

Table 6. Block Transfer Instructions

Mnemonic Operands Instruction


LDCI dst, src Load Constant to/from Program Memory and Auto-Increment Addresses

LDEI dst, src Load External Data to/from Data Memory and Auto-Increment

Addresses

Table 7. CPU Control Instructions

Mnemonic Operands Instruction

CCF — Complement Carry Flag

DI — Disable Interrupts

EI — Enable Interrupts

HALT — HALT Mode

NOP — No Operation

RCF — Reset Carry Flag

SCF — Set Carry Flag

SRP src Set Register Pointer

Table 7. CPU Control Instructions (Continued)

Mnemonic Operands Instruction
STOP — STOP Mode

WDT — Watch-Dog Timer Refresh


Table 8. Load Instructions

Mnemonic Operands Instruction


CLR dst Clear

LD dst, src Load

LDC dst, src Load Constant to/from Program Memory

LDCI dst, src Load Constant to/from Program Memory and Auto-Increment

Addresses

Table 8. Load Instructions (Continuing)

Mnemonic Operands Instruction


LDE dst, src Load External Data to/from Data Memory

LDEI dst, src Load External Data to/from Data Memory and Auto-Increment

Addresses

LDX dst, src Load using Extended Addressing

LEA dst, X(src) Load Effective Address

POP dst Pop

POPX dst Pop using Extended Addressing

PUSH src Push

PUSHX src Push using Extended Addressing

Table 9. Logical Instructions

Mnemonic Operands Instruction


AND dst, src Logical AND

ANDX dst, src Logical AND using Extended Addressing

COM dst Complement

OR dst, src Logical OR

ORX dst, src Logical OR using Extended Addressing

XOR dst, src Logical Exclusive OR

XORX dst, src Logical Exclusive OR using Extended Addressing

Table 10. Program Control Instructions

Mnemonic Operands Instruction

BRK — On-Chip Debugger Break

BTJ p, bit, src, DA Bit Test and Jump

BTJNZ bit, src, DA Bit Test and Jump if Non-Zero

BTJZ bit, src, DA Bit Test and Jump if Zero

CALL dst Call Procedure

DJNZ dst, src, RA Decrement and Jump Non-Zero

IRET — Interrupt Return

JP dst Jump

JP cc dst Jump Conditional

JR DA Jump Relative

JR cc DA Jump Relative Conditional

RET — Return

TRAP vector Software Trap



Table 11. Rotate and Shift Instructions

Mnemonic Operands Instruction


BSWAP dst Bit Swap

RL dst Rotate Left

RLC dst Rotate Left through Carry

RR dst Rotate Right

RRC dst Rotate Right through Carry

SRA dst Shift Right Arithmetic

SRL dst Shift Right Logical

SWAP dst Swap Nibbles



1.2.5. Flags Register


The Flags Register contains the status information regarding the most recent arithmetic, logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z and S) can be tested for use with conditional jump instructions. Two flags (H and D) cannot be tested and are used for Binary-Coded Decimal (BCD) arithmetic. The two remaining bits, User Flags (F1 and F2), are available as general-purpose status bits. User Flags are unaffected by arithmetic operations and must be set or cleared by instructions. The User Flags cannot be used with conditional Jumps. They are undefined at initial power-up and are unaffected by Reset. Figure 2 illustrates the flags and their bit positions in the Flags Register.



Figure 2. Flags Register
Interrupts, the Software Trap (TRAP) instruction, and Illegal Instruction Traps all write the value of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruction restores the value saved on the stack into the Flags Register.
1.3. INSTALLING ZDS II

Perform the following procedure to install ZDS II:

1. Insert the CD in your CD-ROM drive.

2. Follow the setup instructions on your screen.

The installer displays a default location for ZDS II. You can change the location if you want to.


1.3.1. Developer’s environment tutorial

This quick tour shows you how to use the Z8 Encore! developer’s environment. In order to begin this tour, you need a basic understanding of Microsoft Windows and a basic under-standing of Microsoft Developer’s Studio. Estimated time for completing this exercise is 15 minutes. In this tour, you do the following:

•“Create a New Project”

•“Add a File to the Project”

•“Set Up the Project”

•“Save the Project”

When you complete this tour, you have a sample.lod file that is used in the Debugging Quick Tour.

1.3.2. Sample Program

For the purpose of this quick tour, your Z8 Encore! developer’s environment directory is ZILOGINSTALL\ZDSII_product_version\ where

ZILOGINSTALL is the ZDS II installation directory. For example, the default installation directory is C:\Program Files\ZiLOG.

product is the specific ZiLOG product. For example, product can be Z8Encore!, eZ80Acclaim!, Crimzon, or Z8GP.

version is the ZDS II version number. For example, version might be 4.8.0 or 4.9.0.

The sample file is main.c.



1.3.3. Create a New Project

1. To create a new project, select New Project from the File menu. The New Project dialog box is displayed.

2.From the New Project dialog box, click on the Browse button () to navigate to the directory where you want your project to reside (Figure 3). For this quick tour, place your project in the following directory:

ZILOGINSTALL\ZDSII_product_version\applications\productfamily\productfamily_uartcode where –ZILOGINSTALL is the ZDS II installation directory. For example, the default installation directory is C:\Program Files\ZiLOG.–product is the specific ZiLOG product. For example, product can be Z8Encore!, eZ80Acclaim!, Crimzon, or Z8GP.–version is the ZDS II version number. For example, version might be 4.8.0 or 4.9.0.–productfamily is the specific product family. For example, productfamily might be Z8Encore!_F642X or Z8Encore!_F04xA.The following is an example of the whole path: C:\Program Files\ZiLOG\ZDSII_Z8Encore!_4.9.1\applications\Z8 Encore! _F642X\ Z8Encore!F642x_uartcode

3. In the File Name field, type the name of your project. Name this project sample. The Z8 Encore! developer’s environment creates a project file. Project files have the .zdsproj extension and are typically named after your project's name. You do not have to type the extension .zdsproj. It is added automatically.

4.Click Select to return to the New Project dialog box.

5. Select the appropriate CPU family and CPU in the CPU Family and CPU drop-down list boxes.

6. Make sure that Executable is selected in the Project Type drop-down list box. See Figure 4.

The default is to create an IEEE 695 executable format (.lod). For more information, see “Linker Tab”.

7. Click Continue.The Configure New Project dialog box is displayed.

8. Click Next.

9. Click Finish. ZDS II creates a new project and adds a file, zsldevinit.asm, to the project in the Project Workspace window. See Figure 5.


Figure 3. Select Project Name Dialog Box



Figure 4. New Project Dialog Box



Figure 5. Configure New Project Dialog Box—Step 1

NOTES: This file, zsldevinit.asm, is a ZiLOG Standard Library (ZSL) device initialization file that initializes the UART and required GPIO devices. For more information on ZSL, see the ZSL API Reference Manual (RM0038).


1.3.4. Add a File to the Project

In this section, you add the main.c file to the sample project.

1. From the Project menu, select Add Files. The Add Files to Project dialog box is displayed.

2.In the Add Files to Project dialog box, navigate to the following directory: ZILOGINSTALL\ZDSII_product_version\applications\productfamily\productfamily_uartcode where –ZILOGINSTALL is the ZDS II installation directory. For example, the default installation directory is C:\Program Files\ZiLOG.–product is the specific ZiLOG product. For example, product can be Z8Encore!, eZ80Acclaim!, Crimzon, or Z8GP.–version is the ZDS II version number. For example, version might be 4.8.0 or 4.9.0. –productfamily is the specific product family. For example, productfamily might be Z8Encore!_F642X or Z8Encore!_F04xA. The following is an example of the whole path: C:\Program Files\ZiLOG\ZDSII_Z8 Encore!_4.9.1\applications\Z8Encore!_F642X\Z8 Encore!F642x_uartcode

3. Select the main.c file and click Add (see Figure 6).

NOTES: To view any of the files in the Edit window during the quick tour, double-click on the file in the Project Workspace window. To delete a file from a project, select the file in the tree view and press Alt+Delete.




Figure 6. Sample Project


1.3.5. Set Up the Project

Before you save and build the sample project, check the settings in the Project Settings dialog box.

1. From the Project menu, select Settings. The Project Settings dialog box includes six tabs you must go through to set up the project settings. Within the C (Compiler) and Linker tabs are categories that allow you to set up subsettings on that specific tab’s category. For more information, see “Settings”.

2. In the drop-down list box in the upper left corner of the Project Settings dialog box, make sure Debug is selected (Figure 7). For your convenience, the Debug configuration is a predefined configuration of defaults set for debugging. For more information on project configurations such as adding your own configuration, see “Set Active Configuration”.

3. Click on the C (Compiler) tab.

4. Select the Use Floating Point Library check box. See Figure 8.

5. Select Code Generation from the Category drop-down list box.

6. Select the ANSI Promotions check box. See Figure 9.

7. Click on the ZSL tab.

8. Select the Port A and UART0 check boxes. See Figure 10.

9. Click on the Linker tab.

10. In the Output category, make certain that only the IEEE 695 check box is selected. See Figure 11.






Figure 7. General Tab in Project Settings Dialog Box



Figure 8. C Tab (General Category) in Project Settings Dialog Box




Figure 9. C Tab (Code Generation Category) in Project Settings Dialog Box



Figure 10. ZSL Tab in Project Settings Dialog Box



Figure 11. Output Category of the Linker Tab



Figure 12. Build Output Window

The executable format defaults to IEEE 695 when you create an executable project (.lod). To change the executable format, see “Linker Tab”.

11. Click OK to save all the settings on the Project Settings dialog box.

12. Click Yes to the warning message saying, “The project settings have changed since the last build. Would you like to rebuild the affected files?” The developer’s environment builds the sample project. 13. Watch the compilation process in the Build Output window (see Figure 12).


When the Build completed message is displayed in the Build Output window, you have successfully built the sample project and created a sample.lod file to debug in the Debugging Quick Tour.

1.3.6. Save the Project


You need to save your project. From the File menu, select Save Project.

1.4. DEBUGGING QUICK TOUR

This tour is designed to acquaint you with the Z8 Encore! developer’s environment debugger. You must have an executable file called sample.lod before continuing with this quick tour. By completing the steps in the previous tour, the system creates a sample.lod file in the following directory: ZILOGINSTALL\ZDSII_product_version\applications\productfamily\productfamily_uartcode\src

Where:

ZILOGINSTALL is the ZDS II installation directory. For example, the default installation directory is C:\Program Files\ZiLOG.



product is the specific ZiLOG product. For example, product can be Z8Encore!, eZ80Acclaim!, Crimzon, or Z8GP.

version is the ZDS II version number. For example, version might be 4.8.0 or 4.9.0.

productfamily is the specific product family. For example, productfamily might be Z8Encore! F642X or Z8Encore! F04xA.The following is an example of the whole path: C:\Program Files\ZiLOG \ZDSII_Z8Encore!_4.9.1\applications\Z8Encore!_F642X\Z8Encore!F642x_uartcode\src

Estimated time for completing this exercise is 15 minutes. Before doing this tour, read “Main Components,” to learn more about the Debug toolbar and Debug Windows toolbar. In this tour, you do the following:

•“Set Up the Debugger”

•“Switch to Debug Mode”

•“Set a Breakpoint”

•“Disassemble the Code”


1.4.1. Set Up the Debugger

Drivers are used to manage communication between your PC and the target device. A target device can be either an emulator or a simulator. By selecting a driver in the Select Target area of the Debugger tab on the Project Settings dialog box, you define where your code runs. For the purpose of this tour, a default driver has been selected for you. Make sure the default driver, the Z8 Encore! Simulator, is applicable for your intended use. For more information on using the Instruction Set Simulator with the Z8 Encore! developer’s environment, see “Instruction Set Simulator Quick Tour” before returning to the next section of this tour. For more information on using an emulator such as the Z8 Encore! Emulator with the Z8 Encore! developer’s environment, see “Emulator Quick Tour” before returning to the next section of this tour.


1.4.2. Switch to Debug Mode

1.Click the Reset button () on the Build toolbar to switch to Debug mode. In Debug mode, the developer’s environment displays messages in the Debug Output window. The Debug toolbar and Debug Windows toolbar are displayed. The main.c file is opened in the Edit window with the PC code line indicator (yellow arrow) at line 110. Blue dots are displayed to the left of all valid code lines; these are lines where breakpoints can be set, the program can be run to, and so on. The status bar displays the current status of your program’s execution. The status can be STOP, STEP, or RUN. In STOP mode, your program is not executing. In STEP mode, a Step Into, Step Over, or Step Out command is in progress. In RUN mode, a Go command has been issued with no animate active. The status bar is either a box displayed in the upper right corner under the title bar or a horizontal bar under the buttons, depending on your screen resolution. See Figure 13.


1.4.3. Set a Breakpoint

1. Add a breakpoint by doing the following:

a.Click in line 117.

b. Click the Insert/Remove Breakpoint button ().A red octagon is displayed to the left of line 117 to indicate a breakpoint. See Figure 14.You can add a maximum of 64 breakpoints to a program.

2. Click on the Go button (). A yellow arrow is displayed on the red octagon, indicating that the debugger executed the code up to line 117. See Figure 15.



Figure 13. Debug Mode



Figure 14. Active Breakpoint



Figure 15. Code Line Indicator

3. Click the Step Into button () once. The debugger steps into the INIT_FLASH function. The PC code line indicator moves to line 16 of the flash.asm file.

4. Click in line 119 of the main.c file.

5. Click the Run to Cursor button () once. The PC code line indicator moves to line 119 of the main.c file.


1.4.4. Disassemble the Code

Use the following procedure to disassemble the code:

1. From the Debug Windows toolbar, click the Disassembly Window button () to open the Disassembly window (Figure 16). The Disassembly window displays assembly-level code corresponding to the source-level code. The debugger lets you set breakpoints and step the code at the assembly level as well as the C level.



Figure 16. Disassembly Window

2. Close the Disassembly window.

3. Click the Stop Debugging button () to exit the debugger. You have successfully completed the Debugging Quick Tour for the Z8 Encore! developer’s environment.
1.5. FILE TYPES

This section describes the file types used with the ZiLOG Developer Studio II.



.asm – This extension indicates that the file is an assembly language file.

.c This extension indicates that the file is a C source file.

.hex – The linker/locator can generate several different object formats including Intel Hex Records (.hex). Use the Executable Formats area in the Output category on the Linker tab of the Project Settings dialog box to choose this format. See “Executable Formats”.

.lib – Static libraries have the .lib extension and are a collection of .obj files. To create a static library, select New Project from the File menu. In the File Name field, type the name of your library. You do not have to type the extension .lib. The extension is added automatically. The Z8 Encore! developer’s environment creates a library file. See “New Project”.

.libcmd – This extension indicates that the file is a librarian command file.

.linkcmd – This extension indicates that the file is a linker command file, an input file for the linker.

.lis – Select the Generate Compiler Listing File (.lis) check box in the Listing Files category of the C (Compiler) tab of the Project Settings dialog box to tell the compiler to create a list-ing file (with the .lis file extension). All source lines are duplicated in this file, as are any errors encountered by the compiler. See “Generate Compiler Listing File (.lis)”.

.lnk – Before the ZDS II 4.9 release, linker command files had the .lnk extension. These files are displayed as shortcuts in Windows Explorer. You can open and read these files using the ZDS II editor.

.lod – The linker/locator can generate several different object formats including IEEE 695 (.lod). Use the Executable Formats area in the Output category on the Linker tab of the Project Settings dialog box to choose this format. See “Executable Formats”.

.lst – This extension indicates an assembly listing file. To generate an assembly listing file, select the Generate Listing File (.lst) check box of the Assembler tab of the Project Set-tings dialog to tell the assembler to create an assembly listing file. The default is checked. See “Generate Listing File (.lst)”. Select the Generate Listing File (.lst) check box of the Listing Files category of the C (Compiler) tab to tell the compiler whether to keep the assembly source file after compiling your code. This can be useful when you want to inspect or modify the assembly code generated by the compiler. Deselecting this option causes the compiler to remove the .lst file after it has been assembled. See “Generate Listing File (.lst)”. The addresses in the assembly listing are relative. To convert the relative addresses into absolute addresses, use the -relist option for the assembler. See “Source Listing (.lst) Format”. To generate a listing file with absolute addresses (source_file_name.lst), select the Perform Re-List check box and the Generate Map File check box (see “General Category” on page 120). In addition, if your project contains C source files, select the Generate Assembly Source (.src) check box (see “Listing Files Category”).

.mak – This extension indicates that the file is a project make file. The format is <project_name> <current_configuration>.mak. To generate a make file, see “Export Makefile”.

.map – The Generate Map File check box in the General category of the Linker tab on the Project Settings dialog box determines whether the linker generates a link map file each time it is run. The link map file is named your project’s name with the .map extension. See “Generate Map File”, “MAP”, and “How much memory is my program using?”.

.obj – Use the ANSI C-Compiler to convert your C source files with the .c extension into relocatable object modules with the .obj extension. The ANSI C-Compiler can be configured using the Project Settings dialog box (C tab). See “C (Compiler) Tab”. Use the Macro Assembler to translate Z8 Encore! assembly language files with the .asm extension into relocatable object modules with the .obj extension. The Macro Assembler is configured using the Project Settings dialog box (Assembler tab). See “Assembler Tab”. After your relocatable object modules are complete, convert them into an executable program using the linker/locator. .pro. Before the ZDS II 4.9 release, project files had the .pro extension.

.s – This extension indicates that the file is an assembly source file. .src. This extension indicates that the file is an assembly source file that was generated by the compiler.

.srec – The linker/locator can generate several different object formats including Motorola S-Records (.srec). Use the Executable Formats area in the Output category on the Linker tab of the Project Settings dialog box to choose this format. See “Executable Formats”.

.wsp – This extension indicates that the file is a workspace file. From the File menu, select Save Project. Saving your project creates a <name>.wsp file where <name> is your project file name. This .wsp file contains all user interface specific project configuration information such as window and toolbar positions. The .wsp file resides in the same directory as your project file. See “Save Project”.

.zdsproj – Starting with the ZDS II 4.9 release, project files have the .zdsproj extension. and are typically named after your project's name. The Z8 Encore! developer’s environment creates a project file. The .zdsproj file contains configuration information for your project. To create a new project, select New Project from the File menu. In the File Name edit field, type the name of your project. You do not have to type the extension .zdsproj. It is added automatically. See “New Project”.

2. PRELIMINARY WORK

Carefully analyze theory of hardware information of Z8 Encore!® microprocessor and software ZDS II to manipulate procedures of Z8 programming. Prepare individual plan to realize analyses of how operate developing system executing programs written in codes of Z8:

 define files to use for quick tours presented in this manual,

 create folders to store data and results of experiments et cetera.


3. EXPERIMENTAL WORK

3.1. Execute all steps to process “Create a New Project” following the manual.

3.2. Explore operations realizing “Add a File to the Project”.

3.3. Complete experiment doing “Set Up the Project” and “Save the Project”.

3.4. Following instructions of the manual step-by-step explore mode “Debugging quick tour”.
4. RESULTS AND CONCLUSIONS

4.1. Explain each of extension of the files that will be obtained on each step of information transform processing sequence of steps from text file to machine codes in microprocessor.

4.2. Explain the nature of processes of information transform from text files to microprocessor codes.
5. SELF TEST QUESTIONS

5.1. When editing a program, why do we not use a word processor?

5.2. The extension .asm at the end of a file name means which of the following?

a). All smashed and mangled

b). Always save in memory

c). Any Sunday or Monday

d). Assembly language

5.3. What is an assembler?

5.4. What is an operand?

5.5. What is a list file?

5.6. The instruction CLR means which of the following?

a) Clear Carry

b) Clear Control Bit

c) Clear Reverse Carry

d) Create LR checksum

5.7. What is wrong with the following line of code?

CPX AF

5.8. What is the carry flag?



5.9. What is a mnemonic?

5.10. The instruction b means which of the following?

a) Block

b) Borrow

c) Branch

d) Binary value from 0 to 7 (000B to 111B)




REFERENCES


  1. eZ8 CPU User Manual, UM0 12811-0904

  2. High Performance 8-bit Microcontrollers, Z8 Encore! 64K Series, PS0 19908-0404

  3. ZiLOG Developer Studio II – Z8 Encore!, User Manual, UM0 13036 – 0105



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