Abstract: This lab is the implementation of rc5 encryption with pre-round and decryption with post round. The round keys are fixed and the input and output are 64 bits. Procedure




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Lab 3: RC5 Encryption/Decryption

EE4313


Section A

Raphael Kumar 0259929

Mikhail Istomin 0261785

Shing Hiu Cheng 0267834

11/3/05

Abstract:

This lab is the implementation of RC5 encryption with pre-round and decryption with post round. The round keys are fixed and the input and output are 64 bits.



Procedure:

Similar to the previous lab but with pre-round for encryption and post-round for decryption:



For Encryption:

A = A + S[0];

B = B + S[1];

for i=1 to 12 do

A = ((A XOR B) <<< B) + S[2*i];

B = ((B XOR A) <<< A) + S[2*1+1];



For Decryption:

for i = 12 to 1 do

B = ( (B – S[2*i+1]) >>> A ) xor A;

A= ( (A – S[2*i]) >>> B ) xor B;

B = B – S[1];

A = A – S[0];

Another thing different from the previous lab was the implementation of states machines. There are 4 total states:


    • IDLE: Do nothing

    • PRE_ROUND: perform RC5 pre-round operations

    • ROUND_OP: perform RC5 round op

      • remain in this state for twelve clock cycles

    • ST_READY: valid data on the output

For encryption when in the idle state nothing happens and after 1 clock cycle it will go into the Pre-round state. In the pre-round state key S[0] will be added to register A and S[1] will be added to register B. Then it moves to the round op state where all the main round operations are done. This is done by using a round counter that activates during the round op states and causes it to run 12 times. After all this is done it is now displaying the correct results and is in the ready state. After this is coded then a functional simulation was done with ModelSim, and a synthesis performed with Xilinx Project Navigator, with a timing simulation performed in ModelSim.

Data and Observations:

The code used to perform both the encryption and decryption functions accompanies this document. Below is a snapshot of the functional simulation performed with the encryption code.



The difference between this lab and lab 2 is that operations are run according to states as shown in the functional simulation above. The i_cnt only increments when the state changes from pre-round to round op. The states allow the programmer to see when changes occur so problems can be diagnosed easier; it also makes it clear when the outputs are changing in respect to other operations. This counter runs from 1 (0001) to 13 (1101) and the output is shown in the cycle after it leaves the ready state. The result was correct.

The timing simulation performed gave the following snapshot.

The delay was very low and the initial glitch was just normal glitches that occur when the inputs propagate. The delay was 14 nanoseconds. An examination of the timing and area reports gives the following.


Number of Slices: 364 out of 12288 2%

Number of Slice Flip Flops: 89 out of 24576 0%

Number of 4 input LUTs: 673 out of 24576 2%

Number of bonded IOBs: 131 out of 408 32%

Number of GCLKs: 1 out of 4 25%

According to the timing report, the delay is 37.315 nanoseconds through 46 levels of logic, and the design was given a speed grade of -4. According to the report, 42.6% of the time was spent on logic, while 57.4% was spent on route. The total memory usage is 84400 kilobytes.

For the second exercise, a decryption operation was implemented with a post round. The functional simulation for this operation was performed utilizing the output of the previous operation.

The generated output created by the output of encryption produced the same input that was used for encryption so the result is correct. A timing simulation was performed on the code and the following figure was produced.



According to the timing simulation performed in ModelSim, the delay is 16 nanoseconds. The timing and area reports give the following information.

Number of Slices: 393 out of 12288 3%

Number of Slice Flip Flops: 86 out of 24576 0%

Number of 4 input LUTs: 744 out of 24576 3%

Number of bonded IOBs: 131 out of 408 32%

Number of GCLKs: 1 out of 4 25%

According to the timing report, the total delay of the design is 32.041 nanoseconds through 42 levels of logic, with a speed grade of -4. Of the total delay, 43.5% was spent on logic, and 65.5% spent on route. The total memory usage was 87472 kilobytes. The results show that there are less levels of logic in decryption which corresponds to the lower delay.

The exercise also called for the clock period to be changed from 100 nanoseconds to 10 nanoseconds. The result of this change in clock period is shown below. It can be seen that the program performs very poorly with such a short clock period. The glitches seen do not allow a result to be extracted and the performance is very poor.

Also called for in the exercise was a change in the speed grade to -6 from -4. This change in speed resulted in the inability of the program to function correctly. The device could not provide the required tasks quickly enough for and when the output was supposedly ready, the output cipher text could not be read.




Conclusion:

Besides having to figure out the nuances of VHDL coding to suit our needs, there were not a lot of difficulties to deal with. One of the only difficulties was that the state had to match the operations done, that problem was solved using conditional statements. The change in frequency to a shorter clock period resulted in diminished performance that does not perform adequately. Also, the change of the speed grade to a lower speed resulted in a change in the performance of the program. It can be inferred from the lab that the speed of the device is very important for it to perform the needed operations and that a clock period should be long enough to overcome the unavoidable glitches for each operation. Overall this lab provided a good understanding of the RC5 state machine.



RC5_ENC.VHD
--A = A + S[0];

--B = B + S[1];

--for i=1 to 12 do

-- A = ((A XOR B) <<< B) + S[2*i];

-- B = ((B XOR A) <<< A) + S[2*1+1];

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY rc5_enc IS

PORT


(

clr : IN STD_LOGIC;

clk : IN STD_LOGIC;

din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);

di_vld : IN STD_LOGIC; -- input is valid

dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);

do_rdy : OUT STD_LOGIC -- output is ready

);

END rc5_enc;


ARCHITECTURE rtl OF rc5_enc IS

SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter


SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor: STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B

-- define a type for round keys

TYPE rom IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR(31 DOWNTO 0);

--instantiate round key rom with 26 round keys

CONSTANT skey : rom:=rom'(X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5",

X"460C6085", X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",

X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D", X"4B792F99",

X"2799A4DD", X"A7901C49", X"DEDE871A", X"36C03196", X"A7EFC249",

X"61A78BB8", X"3B0A1D2B", X"4DBFCA76", X"AE162167", X"30D76B0A",

X"43192304", X"F6CC1431", X"65046380");


-- RC5 state machine has five states

TYPE StateType IS ( ST_IDLE, --

ST_PRE_ROUND, -- in this state RC5 pre-round op is performed

ST_ROUND_OP, -- in this state RC5 round op is performed. The state machine remains in this state for twelve clock cycles.

ST_READY --

);

-- RC5 state machine has five states: idle, pre_round, round and ready



SIGNAL state : StateType;
BEGIN

-- A=((A XOR B)<<
ab_xor <= a_reg XOR b_reg;
WITH b_reg(4 DOWNTO 0) SELECT

a_rot<=ab_xor(30 DOWNTO 0) & ab_xor(31) WHEN "00001",

ab_xor(29 DOWNTO 0) & ab_xor(31 DOWNTO 30) WHEN "00010",

ab_xor(28 DOWNTO 0) & ab_xor(31 DOWNTO 29) WHEN "00011",

ab_xor(27 DOWNTO 0) & ab_xor(31 DOWNTO 28) WHEN "00100",

ab_xor(26 DOWNTO 0) & ab_xor(31 DOWNTO 27) WHEN "00101",

ab_xor(25 DOWNTO 0) & ab_xor(31 DOWNTO 26) WHEN "00110",

ab_xor(24 DOWNTO 0) & ab_xor(31 DOWNTO 25) WHEN "00111",

ab_xor(23 DOWNTO 0) & ab_xor(31 DOWNTO 24) WHEN "01000",

ab_xor(22 DOWNTO 0) & ab_xor(31 DOWNTO 23) WHEN "01001",

ab_xor(21 DOWNTO 0) & ab_xor(31 DOWNTO 22) WHEN "01010",

ab_xor(20 DOWNTO 0) & ab_xor(31 DOWNTO 21) WHEN "01011",

ab_xor(19 DOWNTO 0) & ab_xor(31 DOWNTO 20) WHEN "01100",

ab_xor(18 DOWNTO 0) & ab_xor(31 DOWNTO 19) WHEN "01101",

ab_xor(17 DOWNTO 0) & ab_xor(31 DOWNTO 18) WHEN "01110",

ab_xor(16 DOWNTO 0) & ab_xor(31 DOWNTO 17) WHEN "01111",

ab_xor(15 DOWNTO 0) & ab_xor(31 DOWNTO 16) WHEN "10000",

ab_xor(14 DOWNTO 0) & ab_xor(31 DOWNTO 15) WHEN "10001",

ab_xor(13 DOWNTO 0) & ab_xor(31 DOWNTO 14) WHEN "10010",

ab_xor(12 DOWNTO 0) & ab_xor(31 DOWNTO 13) WHEN "10011",

ab_xor(11 DOWNTO 0) & ab_xor(31 DOWNTO 12) WHEN "10100",

ab_xor(10 DOWNTO 0) & ab_xor(31 DOWNTO 11) WHEN "10101",

ab_xor(9 DOWNTO 0) & ab_xor(31 DOWNTO 10) WHEN "10110",

ab_xor(8 DOWNTO 0) & ab_xor(31 DOWNTO 9) WHEN "10111",

ab_xor(7 DOWNTO 0) & ab_xor(31 DOWNTO 8) WHEN "11000",

ab_xor(6 DOWNTO 0) & ab_xor(31 DOWNTO 7) WHEN "11001",

ab_xor(5 DOWNTO 0) & ab_xor(31 DOWNTO 6) WHEN "11010",

ab_xor(4 DOWNTO 0) & ab_xor(31 DOWNTO 5) WHEN "11011",

ab_xor(3 DOWNTO 0) & ab_xor(31 DOWNTO 4) WHEN "11100",

ab_xor(2 DOWNTO 0) & ab_xor(31 DOWNTO 3) WHEN "11101",

ab_xor(1 DOWNTO 0) & ab_xor(31 DOWNTO 2) WHEN "11110",

ab_xor(0) & ab_xor(31 DOWNTO 1) WHEN "11111",

ab_xor WHEN OTHERS;
a_pre<=din(63 DOWNTO 32) + skey(0); -- A = A + S[0]

a<=a_rot + skey(CONV_INTEGER(i_cnt & '0')); -- S[2*i]


-- B=((B XOR A) <<ba_xor <= b_reg XOR a;

WITH a(4 DOWNTO 0) SELECT


b_rot<=ba_xor(30 DOWNTO 0) & ba_xor(31) WHEN "00001",

ba_xor(29 DOWNTO 0) & ba_xor(31 DOWNTO 30) WHEN "00010",

ba_xor(28 DOWNTO 0) & ba_xor(31 DOWNTO 29) WHEN "00011",

ba_xor(27 DOWNTO 0) & ba_xor(31 DOWNTO 28) WHEN "00100",

ba_xor(26 DOWNTO 0) & ba_xor(31 DOWNTO 27) WHEN "00101",

ba_xor(25 DOWNTO 0) & ba_xor(31 DOWNTO 26) WHEN "00110",

ba_xor(24 DOWNTO 0) & ba_xor(31 DOWNTO 25) WHEN "00111",

ba_xor(23 DOWNTO 0) & ba_xor(31 DOWNTO 24) WHEN "01000",

ba_xor(22 DOWNTO 0) & ba_xor(31 DOWNTO 23) WHEN "01001",

ba_xor(21 DOWNTO 0) & ba_xor(31 DOWNTO 22) WHEN "01010",

ba_xor(20 DOWNTO 0) & ba_xor(31 DOWNTO 21) WHEN "01011",

ba_xor(19 DOWNTO 0) & ba_xor(31 DOWNTO 20) WHEN "01100",

ba_xor(18 DOWNTO 0) & ba_xor(31 DOWNTO 19) WHEN "01101",

ba_xor(17 DOWNTO 0) & ba_xor(31 DOWNTO 18) WHEN "01110",

ba_xor(16 DOWNTO 0) & ba_xor(31 DOWNTO 17) WHEN "01111",

ba_xor(15 DOWNTO 0) & ba_xor(31 DOWNTO 16) WHEN "10000",

ba_xor(14 DOWNTO 0) & ba_xor(31 DOWNTO 15) WHEN "10001",

ba_xor(13 DOWNTO 0) & ba_xor(31 DOWNTO 14) WHEN "10010",

ba_xor(12 DOWNTO 0) & ba_xor(31 DOWNTO 13) WHEN "10011",

ba_xor(11 DOWNTO 0) & ba_xor(31 DOWNTO 12) WHEN "10100",

ba_xor(10 DOWNTO 0) & ba_xor(31 DOWNTO 11) WHEN "10101",

ba_xor(9 DOWNTO 0) & ba_xor(31 DOWNTO 10) WHEN "10110",

ba_xor(8 DOWNTO 0) & ba_xor(31 DOWNTO 9) WHEN "10111",

ba_xor(7 DOWNTO 0) & ba_xor(31 DOWNTO 8) WHEN "11000",

ba_xor(6 DOWNTO 0) & ba_xor(31 DOWNTO 7) WHEN "11001",

ba_xor(5 DOWNTO 0) & ba_xor(31 DOWNTO 6) WHEN "11010",

ba_xor(4 DOWNTO 0) & ba_xor(31 DOWNTO 5) WHEN "11011",

ba_xor(3 DOWNTO 0) & ba_xor(31 DOWNTO 4) WHEN "11100",

ba_xor(2 DOWNTO 0) & ba_xor(31 DOWNTO 3) WHEN "11101",

ba_xor(1 DOWNTO 0) & ba_xor(31 DOWNTO 2) WHEN "11110",

ba_xor(0) & ba_xor(31 DOWNTO 1) WHEN "11111",

ba_xor WHEN OTHERS;


b_pre <= din(31 DOWNTO 0) + skey(1); -- B = B + S[1]

b<=b_rot + skey(CONV_INTEGER(i_cnt & '1')); -- S[2*i+1]


-- A register

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

a_reg<=(OTHERS=>'0');

ELSIF(clk'EVENT AND clk='1') THEN

IF(state=ST_PRE_ROUND) THEN a_reg<=a_pre;

ELSIF(state=ST_ROUND_OP) THEN a_reg<=a; END IF;

END IF;


END PROCESS;
-- B register

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

b_reg<=(OTHERS=>'0');

ELSIF(clk'EVENT AND clk='1') THEN

IF(state=ST_PRE_ROUND) THEN b_reg<=b_pre;

ELSIF(state=ST_ROUND_OP) THEN b_reg<=b; END IF;

END IF;


END PROCESS;

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

state<=ST_IDLE;

ELSIF(clk'EVENT AND clk='1') THEN

CASE state IS

WHEN ST_IDLE=> IF(di_vld='1') THEN state<=ST_PRE_ROUND; END IF;

WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;

WHEN ST_ROUND_OP=> IF(i_cnt="1100") THEN state<=ST_READY; END IF;

WHEN ST_READY=> state<=ST_IDLE;

END CASE;

END IF;


END PROCESS;
-- round counter

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

i_cnt<="0001";

ELSIF(clk'EVENT AND clk='1') THEN

IF(state=ST_ROUND_OP) THEN

IF(i_cnt="1100") THEN i_cnt<="0001";

ELSE i_cnt<=i_cnt+'1'; END IF;

END IF;

END IF;


END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT

do_rdy<= '1' WHEN ST_READY,

'0' WHEN OTHERS;

END rtl;


RC5_DEC,VHD
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER

ENTITY rc5_dec IS

PORT

(

clr : IN STD_LOGIC; -- Asynchronous reset



clk : IN STD_LOGIC; -- Clock signal

di_vld : IN STD_LOGIC;

din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input

dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output

do_rdy : OUT STD_LOGIC

);

END rc5_dec;



ARCHITECTURE rtl OF rc5_dec IS

SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter

SIGNAL bskey_minus : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a_post : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A

--SIGNAL ba_xor: STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL askey_minus : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b_post : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
-- define a type for round keys

TYPE rom IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR(31 DOWNTO 0);

--instantiate round key rom with 26 round keys

CONSTANT skey : rom:=rom'(X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5",

X"460C6085", X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",

X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D", X"4B792F99",

X"2799A4DD", X"A7901C49", X"DEDE871A", X"36C03196", X"A7EFC249",

X"61A78BB8", X"3B0A1D2B", X"4DBFCA76", X"AE162167", X"30D76B0A",

X"43192304", X"F6CC1431", X"65046380");

-- RC5 state machine has five states

TYPE StateType IS ( ST_IDLE, --

--ST_POST_ROUND, -- in this state RC5 post-round op is performed

ST_ROUND_OP, -- in this state RC5 round op is performed. The state machine remains in this state for twelve clock cycles.

ST_READY --

);

-- RC5 state machine has five states: idle, pre_round, round and ready



SIGNAL state : StateType;
BEGIN

-- B=((B - S[2*i+1]) >>> A) XOR A


bskey_minus<=b_reg - skey(CONV_INTEGER(i_cnt & '1')); -- S[2*i+1]

WITH a_reg(4 DOWNTO 0) SELECT

b_rot<= bskey_minus(0) & bskey_minus (31 DOWNTO 1) WHEN "00001",

bskey_minus(1 DOWNTO 0) & bskey_minus (31 DOWNTO 2) WHEN "00010",

bskey_minus(2 DOWNTO 0) & bskey_minus (31 DOWNTO 3) WHEN "00011",

bskey_minus(3 DOWNTO 0) & bskey_minus (31 DOWNTO 4) WHEN "00100",

bskey_minus(4 DOWNTO 0) & bskey_minus (31 DOWNTO 5) WHEN "00101",

bskey_minus(5 DOWNTO 0) & bskey_minus (31 DOWNTO 6) WHEN "00110",

bskey_minus(6 DOWNTO 0) & bskey_minus (31 DOWNTO 7) WHEN "00111",

bskey_minus(7 DOWNTO 0) & bskey_minus (31 DOWNTO 8) WHEN "01000",

bskey_minus(8 DOWNTO 0) & bskey_minus (31 DOWNTO 9) WHEN "01001",

bskey_minus(9 DOWNTO 0) & bskey_minus (31 DOWNTO 10) WHEN "01010",

bskey_minus(10 DOWNTO 0) & bskey_minus (31 DOWNTO 11) WHEN "01011",

bskey_minus(11 DOWNTO 0) & bskey_minus (31 DOWNTO 12) WHEN "01100",

bskey_minus(12 DOWNTO 0) & bskey_minus (31 DOWNTO 13) WHEN "01101",

bskey_minus(13 DOWNTO 0) & bskey_minus (31 DOWNTO 14) WHEN "01110",

bskey_minus(14 DOWNTO 0) & bskey_minus (31 DOWNTO 15) WHEN "01111",

bskey_minus(15 DOWNTO 0) & bskey_minus (31 DOWNTO 16) WHEN "10000",

bskey_minus(16 DOWNTO 0) & bskey_minus (31 DOWNTO 17) WHEN "10001",

bskey_minus(17 DOWNTO 0) & bskey_minus (31 DOWNTO 18) WHEN "10010",

bskey_minus(18 DOWNTO 0) & bskey_minus (31 DOWNTO 19) WHEN "10011",

bskey_minus(19 DOWNTO 0) & bskey_minus (31 DOWNTO 20) WHEN "10100",

bskey_minus(20 DOWNTO 0) & bskey_minus (31 DOWNTO 21) WHEN "10101",

bskey_minus(21 DOWNTO 0) & bskey_minus (31 DOWNTO 22) WHEN "10110",

bskey_minus(22 DOWNTO 0) & bskey_minus (31 DOWNTO 23) WHEN "10111",

bskey_minus(23 DOWNTO 0) & bskey_minus (31 DOWNTO 24) WHEN "11000",

bskey_minus(24 DOWNTO 0) & bskey_minus (31 DOWNTO 25) WHEN "11001",

bskey_minus(25 DOWNTO 0) & bskey_minus (31 DOWNTO 26) WHEN "11010",

bskey_minus(26 DOWNTO 0) & bskey_minus (31 DOWNTO 27) WHEN "11011",

bskey_minus(27 DOWNTO 0) & bskey_minus (31 DOWNTO 28) WHEN "11100",

bskey_minus(28 DOWNTO 0) & bskey_minus (31 DOWNTO 29) WHEN "11101",

bskey_minus(29 DOWNTO 0) & bskey_minus (31 DOWNTO 30) WHEN "11110",

bskey_minus(30 DOWNTO 0) & bskey_minus (31) WHEN "11111",

bskey_minus WHEN OTHERS;

b <= b_rot XOR a_reg;

b_post <= b_reg - skey(1); --B = B - S[1]

-- A=((A - S[2*i]) >>> B) XOR B;

askey_minus<=a_reg - skey(CONV_INTEGER(i_cnt & '0'));

WITH b(4 DOWNTO 0) SELECT

a_rot <= askey_minus(0) & askey_minus (31 DOWNTO 1) WHEN "00001",

askey_minus(1 DOWNTO 0) & askey_minus (31 DOWNTO 2) WHEN "00010",

askey_minus(2 DOWNTO 0) & askey_minus (31 DOWNTO 3) WHEN "00011",

askey_minus(3 DOWNTO 0) & askey_minus (31 DOWNTO 4) WHEN "00100",

askey_minus(4 DOWNTO 0) & askey_minus (31 DOWNTO 5) WHEN "00101",

askey_minus(5 DOWNTO 0) & askey_minus (31 DOWNTO 6) WHEN "00110",

askey_minus(6 DOWNTO 0) & askey_minus (31 DOWNTO 7) WHEN "00111",

askey_minus(7 DOWNTO 0) & askey_minus (31 DOWNTO 8) WHEN "01000",

askey_minus(8 DOWNTO 0) & askey_minus (31 DOWNTO 9) WHEN "01001",

askey_minus(9 DOWNTO 0) & askey_minus (31 DOWNTO 10) WHEN "01010",

askey_minus(10 DOWNTO 0) & askey_minus (31 DOWNTO 11) WHEN "01011",

askey_minus(11 DOWNTO 0) & askey_minus (31 DOWNTO 12) WHEN "01100",

askey_minus(12 DOWNTO 0) & askey_minus (31 DOWNTO 13) WHEN "01101",

askey_minus(13 DOWNTO 0) & askey_minus (31 DOWNTO 14) WHEN "01110",

askey_minus(14 DOWNTO 0) & askey_minus (31 DOWNTO 15) WHEN "01111",

askey_minus(15 DOWNTO 0) & askey_minus (31 DOWNTO 16) WHEN "10000",

askey_minus(16 DOWNTO 0) & askey_minus (31 DOWNTO 17) WHEN "10001",

askey_minus(17 DOWNTO 0) & askey_minus (31 DOWNTO 18) WHEN "10010",

askey_minus(18 DOWNTO 0) & askey_minus (31 DOWNTO 19) WHEN "10011",

askey_minus(19 DOWNTO 0) & askey_minus (31 DOWNTO 20) WHEN "10100",

askey_minus(20 DOWNTO 0) & askey_minus (31 DOWNTO 21) WHEN "10101",

askey_minus(21 DOWNTO 0) & askey_minus (31 DOWNTO 22) WHEN "10110",

askey_minus(22 DOWNTO 0) & askey_minus (31 DOWNTO 23) WHEN "10111",

askey_minus(23 DOWNTO 0) & askey_minus (31 DOWNTO 24) WHEN "11000",

askey_minus(24 DOWNTO 0) & askey_minus (31 DOWNTO 25) WHEN "11001",

askey_minus(25 DOWNTO 0) & askey_minus (31 DOWNTO 26) WHEN "11010",

askey_minus(26 DOWNTO 0) & askey_minus (31 DOWNTO 27) WHEN "11011",

askey_minus(27 DOWNTO 0) & askey_minus (31 DOWNTO 28) WHEN "11100",

askey_minus(28 DOWNTO 0) & askey_minus (31 DOWNTO 29) WHEN "11101",

askey_minus(29 DOWNTO 0) & askey_minus (31 DOWNTO 30) WHEN "11110",

askey_minus(30 DOWNTO 0) & askey_minus (31) WHEN "11111",

askey_minus WHEN OTHERS;

a <= a_rot XOR b;

a_post <= a_reg - skey(0); --A = A - S[0]

-- A register

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

a_reg<=din(63 DOWNTO 32);

ELSIF(clk'EVENT AND clk='1') THEN

IF(state=ST_ROUND_OP) THEN a_reg<=a; END IF;

END IF;


END PROCESS;
-- B register

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

b_reg<=din(31 DOWNTO 0);

ELSIF(clk'EVENT AND clk='1') THEN

IF(state=ST_ROUND_OP) THEN b_reg<=b; END IF;

END IF;

END PROCESS;



PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

state<=ST_IDLE;

ELSIF(clk'EVENT AND clk='1') THEN

CASE state IS

WHEN ST_IDLE=> IF(di_vld='1') THEN state<=ST_ROUND_OP; END IF;

--WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;

WHEN ST_ROUND_OP=> IF(i_cnt="0001") THEN state<=ST_READY; END IF;

--WHEN ST_POST_ROUND=> state<=ST_READY;

WHEN ST_READY=> state<=ST_IDLE;

END CASE;

END IF;


END PROCESS;

-- round counter

PROCESS(clr, clk) BEGIN

IF(clr='0') THEN

i_cnt<="1100";

ELSIF(clk'EVENT AND clk='1') THEN

IF(i_cnt="0001") THEN

i_cnt<="1100";

ELSE

CASE state IS



WHEN ST_ROUND_OP => i_cnt<=i_cnt-'1';

WHEN OTHERS=> NULL;

END CASE;

END IF;


END IF;

END PROCESS;


dout<=a_post & b_post;
WITH state SELECT

do_rdy<= '1' WHEN ST_READY,

'0' WHEN OTHERS;
END rtl;

RC5_ENC TIMING AND AREA REPORT
Release 5.2i - xst F.28

Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to __projnav

CPU : 0.00 / 3.19 s | Elapsed : 0.00 / 3.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 3.19 s | Elapsed : 0.00 / 3.00 s

--> Reading design: rc5_enc.prj
TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) HDL Analysis

4) HDL Synthesis

4.1) HDL Synthesis Report

5) Low Level Synthesis

6) Final Report

6.1) Device utilization summary

6.2) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : rc5_enc.prj

Input Format : VHDL

Ignore Synthesis Constraint File : NO
---- Target Parameters

Output File Name : rc5_enc

Output Format : NGC

Target Device : xcv1000-4bg560


---- Source Options

Entity Name : rc5_enc

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

ROM Style : Auto

Mux Extraction : YES

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

Resource Sharing : YES

Complex Clock Enable Extraction : YES

Multiplier Style : lut

Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 100

Add Generic Clock Buffer(BUFG) : 4

Register Duplication : YES

Equivalent register Removal : YES

Slice Packing : YES

Pack IO Registers into IOBs : auto


---- General Options

Optimization Criterion : Speed

Optimization Effort : 1

Keep Hierarchy : NO

Global Optimization : AllClockNets

RTL Output : Yes

Write Timing Constraints : NO

Hierarchy Separator : _

Bus Delimiter : <>

Case Specifier : lower

Top module area constraint : 100

Top module allowed area overflow : 5


---- Other Options

read_cores : YES

cross_clock_analysis : NO
=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling vhdl file C:/raph/rc5_enc/../rc5_enc.vhd in Library work.

Architecture rtl of Entity rc5_enc is up to date.


=========================================================================

* HDL Analysis *

=========================================================================
Analyzing Entity (Architecture ).

WARNING:Xst:790 - C:/raph/rc5_enc/../rc5_enc.vhd line 97: Index value(s) does not match array range, simulation mismatch.

WARNING:Xst:790 - C:/raph/rc5_enc/../rc5_enc.vhd line 138: Index value(s) does not match array range, simulation mismatch.

Entity analyzed. Unit generated.

=========================================================================

* HDL Synthesis *

=========================================================================
Synthesizing Unit .

Related source file is C:/raph/rc5_enc/../rc5_enc.vhd.

Found 26x32-bit ROM for signal <$n0004> created at line 97.

Found 26x32-bit ROM for signal <$n0005> created at line 138.

Found finite state machine for signal .

-----------------------------------------------------------------------

| States | 4 |

| Transitions | 6 |

| Inputs | 2 |

| Outputs | 4 |

| Reset type | asynchronous |

| Encoding | automatic |

| State register | d flip-flops |

-----------------------------------------------------------------------

Found 32-bit adder for signal .

Found 32-bit adder for signal .

Found 32-bit register for signal .

Found 32-bit shifter rotate left for signal .

Found 32-bit xor2 for signal .

Found 32-bit adder for signal .

Found 32-bit adder for signal .

Found 32-bit register for signal .

Found 32-bit shifter rotate left for signal .

Found 32-bit xor2 for signal .

Found 4-bit up counter for signal .

Summary:


inferred 1 Finite State Machine(s).

inferred 2 ROM(s).

inferred 1 Counter(s).

inferred 64 D-type flip-flop(s).

inferred 4 Adder/Subtracter(s).

inferred 2 Combinational logic shifter(s).

Unit synthesized.

=========================================================================

HDL Synthesis Report
Macro Statistics

# FSMs : 1

# ROMs : 2

26x32-bit ROM : 2

# Registers : 2

32-bit register : 2

# Counters : 1

4-bit up counter : 1

# Logic shifters : 2

32-bit shifter rotate left : 2

# Adders/Subtractors : 4

32-bit adder : 4

# Xors : 2

32-bit xor2 : 2


=========================================================================
Optimizing FSM with One-Hot encoding and d flip-flops.

=========================================================================

* Low Level Synthesis *

=========================================================================

Library "C:/Xilinx/data/librtl.xst" Consulted
Optimizing unit ...
Mapping all equations...

Loading device for application Xst from file 'v1000.nph' in environment C:/Xilinx.

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block rc5_enc, actual ratio is 3.

FlipFlop b_reg_1 has been replicated 3 time(s)

FlipFlop i_cnt_1 has been replicated 1 time(s)

FlipFlop i_cnt_3 has been replicated 1 time(s)

FlipFlop i_cnt_2 has been replicated 1 time(s)

FlipFlop i_cnt_0 has been replicated 1 time(s)

FlipFlop b_reg_3 has been replicated 2 time(s)

FlipFlop b_reg_2 has been replicated 1 time(s)

FlipFlop b_reg_4 has been replicated 1 time(s)

FlipFlop b_reg_0 has been replicated 1 time(s)

FlipFlop i_cnt_0 has been replicated 1 time(s)

FlipFlop i_cnt_1 has been replicated 1 time(s)

FlipFlop i_cnt_3 has been replicated 1 time(s)

FlipFlop i_cnt_2 has been replicated 1 time(s)

FlipFlop state_FFD3 has been replicated 1 time(s)


=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : rc5_enc.ngr

Top Level Output File Name : rc5_enc

Output Format : NGC

Optimization Criterion : Speed

Keep Hierarchy : NO

Macro Generator : macro+


Design Statistics

# IOs : 132


Macro Statistics :

# ROMs : 2

# 26x32-bit ROM : 2

# Registers : 6

# 1-bit register : 4

# 32-bit register : 2

# Logic shifters : 2

# 32-bit shifter rotate left : 2

# Adders/Subtractors : 5

# 32-bit adder : 4

# 4-bit adder : 1
Cell Usage :

# BELS : 1025

# GND : 1

# LUT1 : 66

# LUT2 : 22

# LUT2_D : 1

# LUT2_L : 33

# LUT3 : 196

# LUT3_D : 2

# LUT3_L : 39

# LUT4 : 249

# LUT4_D : 2

# LUT4_L : 63

# MUXCY : 124

# MUXF5 : 102

# VCC : 1

# XORCY : 124

# FlipFlops/Latches : 89

# FDC : 76

# FDCE : 9

# FDP : 1

# FDPE : 3

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 131

# IBUF : 66

# OBUF : 65

=========================================================================


Device utilization summary:

---------------------------


Selected Device : v1000bg560-4
Number of Slices: 364 out of 12288 2%

Number of Slice Flip Flops: 89 out of 24576 0%

Number of 4 input LUTs: 673 out of 24576 2%

Number of bonded IOBs: 131 out of 408 32%

Number of GCLKs: 1 out of 4 25%

=========================================================================

TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP | 89 |

-----------------------------------+------------------------+-------+
Timing Summary:

---------------

Speed Grade: -4
Minimum period: 37.315ns (Maximum Frequency: 26.799MHz)

Minimum input arrival time before clock: 11.145ns

Maximum output required time after clock: 10.324ns

Maximum combinational path delay: No path found


Timing Detail:

--------------

All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clk'

Delay: 37.315ns (Levels of Logic = 46)

Source: b_reg_1

Destination: b_reg_31

Source Clock: clk rising

Destination Clock: clk rising
Data Path: b_reg_1 to b_reg_31

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:c->q 19 1.372 3.410 b_reg_1 (b_reg_1)

LUT2_L:I1->LO 1 0.738 0.100 mshift_a_rot_sh21_sw0 (n13779)

LUT4:i1->o 4 0.738 1.760 mshift_a_rot_sh21 (mshift_a_rot_sh2)

LUT3:i1->o 1 0.738 0.000 mshift_a_rot_sh4011_g (n14050)

MUXF5:i1->o 2 0.173 1.474 mshift_a_rot_sh4011 (mshift_a_rot_sh40)

LUT3_D:I1->O 12 0.738 2.640 ker88651 (n8867)

LUT4_D:I2->LO 1 0.738 0.000 mshift_b_rot_sh191_sw0 (N14612)

MUXCY:s->o 1 0.842 0.000 madd_a_inst_cy_0 (madd_a_inst_cy_0)

MUXCY:ci->o 1 0.057 0.000 madd_a_inst_cy_1 (madd_a_inst_cy_1)

MUXCY:ci->o 1 0.057 0.000 madd_a_inst_cy_2 (madd_a_inst_cy_2)

MUXCY:ci->o 1 0.057 0.000 madd_a_inst_cy_3 (madd_a_inst_cy_3)

XORCY:ci->o 34 0.538 4.290 madd_a_inst_sum_4 (_n0019<4>)

LUT2:i0->o 4 0.738 1.760 mxor_ba_xor_result<4>1 (ba_xor<4>)

LUT4:i1->o 1 0.738 0.000 ker919511_f (n14263)

MUXF5:i0->o 4 0.562 1.760 ker919511 (n9197)

LUT4:i3->o 1 0.738 0.000 mshift_b_rot_sh3711_f (n14233)

MUXF5:i0->o 2 0.562 1.474 mshift_b_rot_sh3711 (mshift_b_rot_sh37)

LUT3:i2->o 2 0.738 1.474 ker91201 (n9122)

LUT4_L:I3->LO 1 0.738 0.000 madd_b_inst_lut2_51 (madd_b_inst_lut2_5)

MUXCY:s->o 1 0.842 0.000 madd_b_inst_cy_5 (madd_b_inst_cy_5)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_6 (madd_b_inst_cy_6)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_7 (madd_b_inst_cy_7)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_8 (madd_b_inst_cy_8)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_9 (madd_b_inst_cy_9)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_10 (madd_b_inst_cy_10)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_11 (madd_b_inst_cy_11)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_12 (madd_b_inst_cy_12)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_13 (madd_b_inst_cy_13)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_14 (madd_b_inst_cy_14)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_15 (madd_b_inst_cy_15)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_16 (madd_b_inst_cy_16)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_17 (madd_b_inst_cy_17)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_18 (madd_b_inst_cy_18)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_19 (madd_b_inst_cy_19)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_20 (madd_b_inst_cy_20)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_21 (madd_b_inst_cy_21)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_22 (madd_b_inst_cy_22)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_23 (madd_b_inst_cy_23)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_24 (madd_b_inst_cy_24)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_25 (madd_b_inst_cy_25)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_26 (madd_b_inst_cy_26)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_27 (madd_b_inst_cy_27)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_28 (madd_b_inst_cy_28)

MUXCY:ci->o 1 0.057 0.000 madd_b_inst_cy_29 (madd_b_inst_cy_29)

MUXCY:ci->o 0 0.057 0.000 madd_b_inst_cy_30 (madd_b_inst_cy_30)

XORCY:ci->o 1 0.538 1.265 madd_b_inst_sum_31 (b<31>)

LUT3_L:I1->LO 1 0.738 0.000 _n0011<31> (_n0011<31>)

FDC:d 0.765 b_reg_31

----------------------------------------

Total 37.315ns (15.908ns logic, 21.407ns route)

(42.6% logic, 57.4% route)
-------------------------------------------------------------------------

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Offset: 11.145ns (Levels of Logic = 2)

Source: clr

Destination: b_reg_20

Destination Clock: clk rising


Data Path: clr to b_reg_20

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:i->o 1 0.989 1.265 clr_ibuf (clr_ibuf)

LUT1:i0->o 89 0.738 7.315 i_cnt_3_aclr_inv1 (i_cnt_0_3_n471)

FDC:clr 0.838 b_reg_20

----------------------------------------

Total 11.145ns (2.565ns logic, 8.580ns route)

(23.0% logic, 77.0% route)


-------------------------------------------------------------------------

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Offset: 10.324ns (Levels of Logic = 1)

Source: b_reg_1_1

Destination: dout<1>

Source Clock: clk rising


Data Path: b_reg_1_1 to dout<1>

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:c->q 18 1.372 3.300 b_reg_1_1 (b_reg_1_1)

OBUF:i->o 5.652 dout_1_obuf (dout<1>)

----------------------------------------

Total 10.324ns (7.024ns logic, 3.300ns route)

(68.0% logic, 32.0% route)
=========================================================================

CPU : 38.95 / 42.54 s | Elapsed : 39.00 / 42.00 s

-->
Total memory usage is 84400 kilobytes


RC5_DEC TIMING AND AREA REPORT
Release 5.2i - xst F.28

Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to __projnav

CPU : 0.00 / 1.54 s | Elapsed : 0.00 / 2.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 1.54 s | Elapsed : 0.00 / 2.00 s

--> Reading design: rc5_dec.prj
TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) HDL Analysis

4) HDL Synthesis

4.1) HDL Synthesis Report

5) Low Level Synthesis

6) Final Report

6.1) Device utilization summary

6.2) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : rc5_dec.prj

Input Format : VHDL

Ignore Synthesis Constraint File : NO
---- Target Parameters

Output File Name : rc5_dec

Output Format : NGC

Target Device : xcv1000-4bg560


---- Source Options

Entity Name : rc5_dec

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

ROM Style : Auto

Mux Extraction : YES

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

Resource Sharing : YES

Complex Clock Enable Extraction : YES

Multiplier Style : lut

Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 100

Add Generic Clock Buffer(BUFG) : 4

Register Duplication : YES

Equivalent register Removal : YES

Slice Packing : YES

Pack IO Registers into IOBs : auto


---- General Options

Optimization Criterion : Speed

Optimization Effort : 1

Keep Hierarchy : NO

Global Optimization : AllClockNets

RTL Output : Yes

Write Timing Constraints : NO

Hierarchy Separator : _

Bus Delimiter : <>

Case Specifier : lower

Top module area constraint : 100

Top module allowed area overflow : 5


---- Other Options

read_cores : YES

cross_clock_analysis : NO
=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling vhdl file C:/raph/decr/rc5_dec/../rc5_dec.vhd in Library work.

Architecture rtl of Entity rc5_dec is up to date.


=========================================================================

* HDL Analysis *

=========================================================================
Analyzing Entity (Architecture ).

WARNING:Xst:790 - C:/raph/decr/rc5_dec/../rc5_dec.vhd line 62: Index value(s) does not match array range, simulation mismatch.

WARNING:Xst:790 - C:/raph/decr/rc5_dec/../rc5_dec.vhd line 101: Index value(s) does not match array range, simulation mismatch.

WARNING:Xst:819 - C:/raph/decr/rc5_dec/../rc5_dec.vhd line 142: The following signals are missing in the process sensitivity list:

din<63>, din<62>, din<61>, din<60>, din<59>, din<58>, din<57>, din<56>, din<55>, din<54>, din<53>, din<52>, din<51>, din<50>, din<49>, din<48>, din<47>, din<46>, din<45>, din<44>, din<43>, din<42>, din<41>, din<40>, din<39>, din<38>, din<37>, din<36>, din<35>, din<34>, din<33>, din<32>.

WARNING:Xst:819 - C:/raph/decr/rc5_dec/../rc5_dec.vhd line 151: The following signals are missing in the process sensitivity list:

din<31>, din<30>, din<29>, din<28>, din<27>, din<26>, din<25>, din<24>, din<23>, din<22>, din<21>, din<20>, din<19>, din<18>, din<17>, din<16>, din<15>, din<14>, din<13>, din<12>, din<11>, din<10>, din<9>, din<8>, din<7>, din<6>, din<5>, din<4>, din<3>, din<2>, din<1>, din<0>.

Entity analyzed. Unit generated.

=========================================================================

* HDL Synthesis *

=========================================================================
Synthesizing Unit .

Related source file is C:/raph/decr/rc5_dec/../rc5_dec.vhd.

Found 26x32-bit ROM for signal <$n0003> created at line 62.

Found 26x32-bit ROM for signal <$n0004> created at line 101.

Found finite state machine for signal .

-----------------------------------------------------------------------

| States | 3 |

| Transitions | 5 |

| Inputs | 2 |

| Outputs | 4 |

| Reset type | asynchronous |

| Encoding | automatic |

| State register | d flip-flops |

-----------------------------------------------------------------------

Found 32-bit xor2 for signal .

Found 32-bit subtractor for signal .

Found 32-bit register for signal .

Found 32-bit shifter rotate right for signal .

Found 32-bit subtractor for signal .

Found 32-bit xor2 for signal .

Found 32-bit subtractor for signal .

Found 32-bit register for signal .

Found 32-bit shifter rotate right for signal .

Found 32-bit subtractor for signal .

Found 4-bit down counter for signal .

Found 64 1-bit 2-to-1 multiplexers.

Summary:

inferred 1 Finite State Machine(s).

inferred 2 ROM(s).

inferred 1 Counter(s).

inferred 4 Adder/Subtracter(s).

inferred 2 Combinational logic shifter(s).

Unit synthesized.

=========================================================================

HDL Synthesis Report
Macro Statistics

# FSMs : 1

# ROMs : 2

26x32-bit ROM : 2

# Registers : 2

32-bit register : 2

# Counters : 1

4-bit down counter : 1

# Multiplexers : 2

2-to-1 multiplexer : 2

# Logic shifters : 2

32-bit shifter rotate right : 2

# Adders/Subtractors : 4

32-bit subtractor : 4

# Xors : 2

32-bit xor2 : 2


=========================================================================
Optimizing FSM with One-Hot encoding and d flip-flops.

=========================================================================

* Low Level Synthesis *

=========================================================================

Library "C:/Xilinx/data/librtl.xst" Consulted
Optimizing unit ...
Mapping all equations...

Loading device for application Xst from file 'v1000.nph' in environment C:/Xilinx.

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block rc5_dec, actual ratio is 3.

FlipFlop i_cnt_3 has been replicated 2 time(s)

FlipFlop i_cnt_2 has been replicated 2 time(s)

FlipFlop i_cnt_0 has been replicated 2 time(s)

FlipFlop i_cnt_1 has been replicated 2 time(s)

FlipFlop a_reg_2_0 has been replicated 3 time(s)

FlipFlop a_reg_0_0 has been replicated 2 time(s)

FlipFlop a_reg_1_0 has been replicated 1 time(s)

FlipFlop a_reg_4_0 has been replicated 1 time(s)


=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : rc5_dec.ngr

Top Level Output File Name : rc5_dec

Output Format : NGC

Optimization Criterion : Speed

Keep Hierarchy : NO

Macro Generator : macro+


Design Statistics

# IOs : 132


Macro Statistics :

# ROMs : 2

# 26x32-bit ROM : 2

# Registers : 12

# 1-bit register : 12

# Logic shifters : 2

# 32-bit shifter rotate right : 2

# Adders/Subtractors : 5

# 32-bit subtractor : 4

# 4-bit subtractor : 1


Cell Usage :

# BELS : 1126

# BUF : 2

# LUT1 : 69

# LUT2 : 160

# LUT2_L : 36

# LUT3 : 285

# LUT3_D : 4

# LUT3_L : 24

# LUT4 : 105

# LUT4_D : 22

# LUT4_L : 39

# MUXCY : 125

# MUXF5 : 122

# VCC : 1

# XORCY : 132

# FlipFlops/Latches : 86

# FDC : 2

# FDCE : 6

# FDCPE : 71

# FDP : 1

# FDPE : 6

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 131

# IBUF : 66

# OBUF : 65

=========================================================================


Device utilization summary:

---------------------------


Selected Device : v1000bg560-4
Number of Slices: 393 out of 12288 3%

Number of Slice Flip Flops: 86 out of 24576 0%

Number of 4 input LUTs: 744 out of 24576 3%

Number of bonded IOBs: 131 out of 408 32%

Number of GCLKs: 1 out of 4 25%

=========================================================================

TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP | 86 |

-----------------------------------+------------------------+-------+
Timing Summary:

---------------

Speed Grade: -4
Minimum period: 32.041ns (Maximum Frequency: 31.210MHz)

Minimum input arrival time before clock: 18.651ns

Maximum output required time after clock: 16.841ns

Maximum combinational path delay: No path found


Timing Detail:

--------------

All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clk'

Delay: 32.041ns (Levels of Logic = 42)

Source: i_cnt_0

Destination: a_reg_0_0

Source Clock: clk rising

Destination Clock: clk rising
Data Path: i_cnt_0 to a_reg_0_0

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDCE:c->q 16 1.372 3.080 i_cnt_0 (i_cnt_0)

LUT4:i0->o 1 0.738 1.265 mrom__n0003_inst_mux_f5_321 (_n0003<0>)

LUT2_L:I1->LO 1 0.738 0.000 msub_bskey_minus_inst_lut2_01 (msub_bskey_minus_inst_lut2_0)

MUXCY:s->o 1 0.842 0.000 msub_bskey_minus_inst_cy_0 (msub_bskey_minus_inst_cy_0)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_1 (msub_bskey_minus_inst_cy_1)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_2 (msub_bskey_minus_inst_cy_2)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_3 (msub_bskey_minus_inst_cy_3)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_4 (msub_bskey_minus_inst_cy_4)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_5 (msub_bskey_minus_inst_cy_5)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_6 (msub_bskey_minus_inst_cy_6)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_7 (msub_bskey_minus_inst_cy_7)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_8 (msub_bskey_minus_inst_cy_8)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_9 (msub_bskey_minus_inst_cy_9)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_10 (msub_bskey_minus_inst_cy_10)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_11 (msub_bskey_minus_inst_cy_11)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_12 (msub_bskey_minus_inst_cy_12)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_13 (msub_bskey_minus_inst_cy_13)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_14 (msub_bskey_minus_inst_cy_14)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_15 (msub_bskey_minus_inst_cy_15)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_16 (msub_bskey_minus_inst_cy_16)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_17 (msub_bskey_minus_inst_cy_17)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_18 (msub_bskey_minus_inst_cy_18)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_19 (msub_bskey_minus_inst_cy_19)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_20 (msub_bskey_minus_inst_cy_20)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_21 (msub_bskey_minus_inst_cy_21)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_22 (msub_bskey_minus_inst_cy_22)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_23 (msub_bskey_minus_inst_cy_23)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_24 (msub_bskey_minus_inst_cy_24)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_25 (msub_bskey_minus_inst_cy_25)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_26 (msub_bskey_minus_inst_cy_26)

MUXCY:ci->o 1 0.057 0.000 msub_bskey_minus_inst_cy_27 (msub_bskey_minus_inst_cy_27)

XORCY:ci->o 4 0.538 1.760 msub_bskey_minus_inst_sum_28 (bskey_minus<28>)

LUT3:i1->o 1 0.738 0.000 ker1285911_f (n16111)

MUXF5:i0->o 5 0.562 1.914 ker1285911 (n12861)

LUT3:i1->o 1 0.738 0.000 ker1235611_f (n15671)

MUXF5:i0->o 3 0.562 1.628 ker1235611 (n12358)

LUT4_D:I3->O 18 0.738 3.300 mxor_b_result<0>1_1 (mxor_b_result<0>1_1)

LUT3:i0->o 4 0.738 1.760 mshift_a_rot_sh410 (mshift_a_rot_sh4)

LUT3:i1->o 1 0.738 0.000 mshift_a_rot_sh3211_f (n16106)

MUXF5:i0->o 4 0.562 1.760 mshift_a_rot_sh3211 (mshift_a_rot_sh32)

LUT3:i2->o 1 0.738 0.000 mshift_a_rot_result<0>11_f (n16006)

MUXF5:i0->o 3 0.562 1.628 mshift_a_rot_result<0>11 (_n0022<32>)

LUT4_L:I3->LO 1 0.738 0.000 mmux__n0008_i31_result1 (_n0008<0>)

FDCPE:d 0.765 a_reg_0_0

----------------------------------------

Total 32.041ns (13.946ns logic, 18.095ns route)

(43.5% logic, 56.5% route)
-------------------------------------------------------------------------

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Offset: 18.651ns (Levels of Logic = 5)

Source: clr

Destination: b_reg_2_0

Destination Clock: clk rising


Data Path: clr to b_reg_2_0

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:i->o 68 0.989 6.160 clr_ibuf (clr_ibuf)

BUF:i->o 68 0.738 6.160 clr_ibuf_1 (clr_ibuf_1)

LUT4:i0->o 1 0.738 0.000 mmux__n0009_i29_result11_f (n15676)

MUXF5:i0->o 3 0.562 1.628 mmux__n0009_i29_result11 (_n0009<2>)

LUT2_L:I1->LO 1 0.738 0.100 b_reg_2__n00001 (b_reg_2__n0000)

FDCPE:clr 0.838 b_reg_2_0

----------------------------------------

Total 18.651ns (4.603ns logic, 14.048ns route)

(24.7% logic, 75.3% route)
-------------------------------------------------------------------------

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Offset: 16.841ns (Levels of Logic = 31)

Source: a_reg_3_0

Destination: dout<63>

Source Clock: clk rising


Data Path: a_reg_3_0 to dout<63>

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDCPE:c->q 45 1.372 4.895 a_reg_3_0 (a_reg_3_0)

LUT1:i0->o 1 0.738 0.000 msub_a_post_inst_lut2_3_rt (msub_a_post_inst_lut2_3_rt)

MUXCY:s->o 1 0.842 0.000 msub_a_post_inst_cy_3 (msub_a_post_inst_cy_3)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_4 (msub_a_post_inst_cy_4)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_5 (msub_a_post_inst_cy_5)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_6 (msub_a_post_inst_cy_6)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_7 (msub_a_post_inst_cy_7)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_8 (msub_a_post_inst_cy_8)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_9 (msub_a_post_inst_cy_9)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_10 (msub_a_post_inst_cy_10)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_11 (msub_a_post_inst_cy_11)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_12 (msub_a_post_inst_cy_12)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_13 (msub_a_post_inst_cy_13)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_14 (msub_a_post_inst_cy_14)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_15 (msub_a_post_inst_cy_15)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_16 (msub_a_post_inst_cy_16)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_17 (msub_a_post_inst_cy_17)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_18 (msub_a_post_inst_cy_18)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_19 (msub_a_post_inst_cy_19)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_20 (msub_a_post_inst_cy_20)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_21 (msub_a_post_inst_cy_21)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_22 (msub_a_post_inst_cy_22)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_23 (msub_a_post_inst_cy_23)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_24 (msub_a_post_inst_cy_24)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_25 (msub_a_post_inst_cy_25)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_26 (msub_a_post_inst_cy_26)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_27 (msub_a_post_inst_cy_27)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_28 (msub_a_post_inst_cy_28)

MUXCY:ci->o 1 0.057 0.000 msub_a_post_inst_cy_29 (msub_a_post_inst_cy_29)

MUXCY:ci->o 0 0.057 0.000 msub_a_post_inst_cy_30 (msub_a_post_inst_cy_30)

XORCY:ci->o 1 0.538 1.265 msub_a_post_inst_sum_31 (dout_63_obuf)

OBUF:i->o 5.652 dout_63_obuf (dout<63>)

----------------------------------------

Total 16.841ns (10.681ns logic, 6.160ns route)

(63.4% logic, 36.6% route)
=========================================================================

CPU : 39.26 / 41.42 s | Elapsed : 39.00 / 41.00 s



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Total memory usage is 87472 kilobytes


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