Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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Дата канвертавання24.04.2016
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spi_if(mac_mosi,3,9,conv_integer(MinSDI_data_v(15 downto 8)));

cs <= '0';

wait for 2*spi_clk_half_period;


cs <= '1';

spi_if(mac_mosi,3,10,conv_integer(MinSDI_data_v(7 downto 0)));

cs <= '0';

wait for 2*spi_clk_half_period; --- added 040210

-------------------------------------------------------------------

elsif ts6 = i then

-- ResONU "00001011" & "00001100"

-------------------------------------------------------------------

cs <= '1';

spi_if(mac_mosi,"00000011","00001011",ResONU_data(15 downto 8));

cs <= '0';

wait for 2*spi_clk_half_period;


cs <= '1';

spi_if(mac_mosi,"00000011","00001100",ResONU_data(7 downto 0));

cs <= '0';

-------------------------------------------------------------------

end if;

i:=i+1;


exit set_data when i = 8;

end loop set_data;

end new_allocID_arrival; --End of Procedure

--translate_on

end package body GMAC_OLT_pkg;

-----------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 11/6/03

-------------------------------------------

-- Design Unit Name :GMAC_OLT

-- Purpose : This entity is the GMAC top level. It includes all the entities

-- that form the GMAC as well as two processes (begining at line 1655

-- that generate two text files that facilitate the debugging.

-- File Name : GMAC_olt_testpins_040206.vhd

-----------------------------------------------------------------------

-----------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use ieee.std_logic_arith.all;


--translate_off

use IEEE.std_logic_textio.all;

--translate_on
library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

--translate_off

library std;

use std.textio.all;

--translate_on


use work.cons_pkg.ALL;

use work.GMAC_OLT_pkg.all;

----------------------------

entity GMAC_OLT is

port(
rstn : IN std_logic;
--OBC i/f

spi_clk : in std_logic; --spi_clk

MAC_mosi : in std_logic; --spi_mosi

MAC_miso : out std_logic; --spi_miso

MAC_cs : in std_logic; --spi_sel

--GXTP i/f

--a. dba report

gxtp_clk : in std_logic;

dba_valid : in std_logic;

dba_bus : in std_logic_vector(11 downto 0);

--b. gxtp sif

gxtp_sif_clk : in std_logic;

gxtp_sif_data : in std_logic;

--c. bandwidth map

BWmap_clk : out std_logic;

BWmap_valid : out std_logic;

BWmap_onuid : out std_logic_vector(1 downto 0);

BWmap_data : out std_logic_vector(15 downto 0);

--TEST PINS

--name : test_xx_module_signalname

--xx = number of pin

--module = name of entity

--signalname = ...<>

test_01_meminit_AllocidValid : OUT std_logic;

test_02_asp_as : OUT std_logic_vector(63 downto 8);

test_03_meminit_BapWe : OUT std_logic;

test_04_asp_AsValid : OUT std_logic;

test_05_asp_GbwStructValid : OUT std_logic;

test_06_asp_OnuPoStructValid : OUT std_logic;

test_07_asp_SbwStructValid : OUT std_logic;

test_08_asp_SpecBroadReq : OUT std_logic;

test_09_asp_GbwStructAllocID : OUT std_logic_vector(9 downto 0);

test_10_asp_GbwStructAllocBytes : OUT std_logic_vector(15 downto 0);

test_11_gbwti_TimersFifoWe : OUT std_logic;

test_12_gbwts_AllocidFetch : OUT std_logic;

test_13_gbwts_AllocidValid : OUT std_logic;

test_14_gbwts_BapAck : OUT std_logic;

test_15_gbwts_BapDataIn : OUT std_logic_vector(47 downto 0);

test_16_onuservice_PLSuPLOAMValid : OUT std_logic;

test_17_onuservice_PLSu_PLOAM : OUT std_logic_vector(1 downto 0);

test_18_sbwts_SbwStructAllocid : OUT std_logic_vector(9 downto 0);

test_19_sbwti_AllocidValid : OUT std_logic;

test_20_crcinsertion_BwmapFifoWe : OUT std_logic;

test_21_crcinsertion_FifoSelecetion : OUT std_logic;

test_22_bwmapforwarder_BwmapFifoRd : OUT std_logic;

test_23_frame_number : OUT std_logic_vector(15 downto 0)

);

end entity GMAC_OLT;


architecture GMAC_OLT_a of GMAC_OLT is
constant zeros48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";

constant zeros21 : std_logic_vector(20 downto 0) := "000000000000000000000";

constant zeros16 : std_logic_vector(15 downto 0) := "0000000000000000";

constant zeros15 : std_logic_vector(14 downto 0) := "000000000000000";

constant zeros12 : std_logic_vector(11 downto 0) := "000000000000";

constant zeros10 : std_logic_vector(9 downto 0) := "0000000000";

constant zeros8 : std_logic_vector(7 downto 0) := "00000000";

constant zeros6 : std_logic_vector(5 downto 0) := "000000";

constant zeros1 : std_logic := '0';
signal clk : std_logic;

-- spi2parallel - parallel_bus i/f

signal spi2parbus_cs : std_logic;

signal spi2parbus_we : std_logic;

signal spi2parbus_addr : std_logic_vector(7 downto 0);

signal spi2parbus_data : std_logic_vector(7 downto 0);

signal parbus2spi_addr : std_logic_vector(7 downto 0);

signal parbus2spi_data : std_logic_vector(7 downto 0);


-- parallel_bus - mem_initializer i/f

signal parbus2meminit_allocid_valid : std_logic;

signal parbus2meminit_allocid : std_logic_vector(allocID_width_con downto 0);

signal parbus2meminit_maxTB : std_logic_vector(TB_width_con - 1 downto 0);

signal parbus2meminit_minTB : std_logic_vector(TB_width_con - 1 downto 0);

signal parbus2meminit_maxSDI : std_logic_vector(SDI_width_con - 1 downto 0);

signal parbus2meminit_minSDI : std_logic_vector(SDI_width_con - 1 downto 0);

signal parbus2meminit_resONU : std_logic_vector(15 downto 0);


-- mem_initializer - minSDI memB (port B)

signal meminit2minsdimemb_addrb : std_logic_vector(allocID_width_con - 1 downto 0);

signal meminit2minsdimemb_datab : std_logic_vector(SDI_mem_width_con - 1 downto 0);

signal meminit2minsdimemb_enb : std_logic;

signal meminit2minsdimemb_web : std_logic;

signal meminit2minsdimemb_web_s : std_logic;

-- mem_initializer - onu_service i/f

signal meminit2onuservice_active_ONUids : std_logic_vector(127 downto 0);

signal meminit2bwmapforwarder_FEC_v : std_logic_vector(127 downto 0);
-- mem_initializer - bap_arbiter i/f

signal meminit2baparb_en : std_logic;

signal meminit2baparb_we : std_logic;

signal meminit2baparb_addr : std_logic_vector(allocID_width_con - 1 downto 0);

signal baparb2meminit_data : std_logic_vector(47 downto 0);
-- mem_initializer - ALMOST ALL ENTITIES

signal fclk_s : std_logic;


-- maxSDI memA portA - gbwti

signal gbwti2maxsdimema_addra : std_logic_vector(allocID_width_con - 1 downto 0);

signal gbwti2maxsdimema_ena : std_logic;

signal gbwti2maxsdimema_wea : std_logic;

signal maxsdimema2gbwti_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);

signal gbwti2maxsdimema_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);


-- maxSDI memB portA - gbwti

signal gbwti2maxsdimemb_addra : std_logic_vector(allocID_width_con - 1 downto 0);

signal gbwti2maxsdimemb_ena : std_logic;

signal gbwti2maxsdimemb_wea : std_logic;

signal maxsdimemb2gbwti_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);

signal gbwti2maxsdimemb_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);

-- gbwti - fifo_maxsdi

signal gbwti2fifo_data : std_logic_vector(allocID_width_con - 1 downto 0);

signal gbwti2fifo_we : std_logic;
-- mux - gbwts i/f

signal afifo2gbwts_allocID : std_logic_vector(allocID_width_con - 1 downto 0);

signal gbwts2afifo_fetch : std_logic;

signal afifo2gbwts_inspection_completed : std_logic;

signal afifo2gbwts_valid : std_logic;
-- gbwts - bap_arbiter & reqmat_arbiter

signal gbwts2baparb_reqmatarb_req : std_logic;

signal gbwts2baparb_reqmatarb_addr : std_logic_vector(allocID_width_con - 1 downto 0);
-- gbwts - bap_arbiter

signal baparb2gbwts_valid : std_logic;

signal baparb2gbwts_data : std_logic_vector(47 downto 0);

signal gbwts2baparb_we : std_logic;


-- gbwts - reqmat_arbiter

signal gbwts2reqmatarb_valid : std_logic;

signal gbwts2reqmatarb_we : std_logic;

signal reqmatarb2gbwts_data : std_logic_vector(reqmat_mem_width_con - 1 downto 0);


-- gbwts - onu_service

signal gbwts2onuservice_req : std_logic;


-- gbwts - asp

signal gbwts2asp_rdy : std_logic;

signal gbwts2asp_allocid : std_logic_vector(allocID_width_con - 1 downto 0);

signal gbwts2asp_onuid : std_logic_vector(7 downto 0);

signal gbwts2asp_alloc_bytes : std_logic_vector(15 downto 0);

signal gbwts2asp_pcbu_fec : std_logic_vector(5 downto 0);

signal gbwts2asp_gbwti_assigned : std_logic;
-- reqmat_arbiter - reqmat_mem

signal reqmatarb2reqmatmem_addr : std_logic_vector(allocID_width_con - 1 downto 0);

signal reqmatarb2reqmatmem_data : std_logic_vector(reqmat_mem_width_con - 1 downto 0);

signal reqmatmem2reqmatarb_data : std_logic_vector(reqmat_mem_width_con - 1 downto 0);

signal reqmatarb2reqmatmem_en : std_logic;

signal reqmatarb2reqmatmem_we : std_logic;


-- bap_arbiter - bap_mem

signal baparb2bapmem_addr : std_logic_vector(allocID_width_con - 1 downto 0);

signal baparb2bapmem_data : std_logic_vector(47 downto 0);

signal bapmem2baparb_data : std_logic_vector(47 downto 0);

signal baparb2bapmem_en : std_logic;

signal baparb2bapmem_we : std_logic;


-- gbw/sbw ts - onu_service i/f

signal ts2onuservice_req : std_logic;

signal ts2onuservice_onuid : std_logic_vector(7 downto 0);
-- onu_service - asp i/f

signal onuservice2asp_struct_valid : std_logic;

signal onuservice2asp_struct_allocID : std_logic_vector(9 downto 0);

signal onuservice2asp_ONU_id : std_logic_vector(7 downto 0);

signal onuservice2asp_alloc_bytes : std_logic_vector(15 downto 0);

signal onuservice2asp_pcbu_fec : std_logic_vector(2 downto 0);

signal onuservice2asp_assigned : std_logic;

signal onuservice2asp_urgent_PLOAM_req : std_logic;


-- onu_service - gxtp_sif

signal gxtpsif2onuservice_onuid : std_logic_vector(7 downto 0);

signal gxtpsif2onuservice_explicit_ploam_req : std_logic;

signal gxtpsif2onuservice_explicit_plsu_req : std_logic;

signal onuservice2gxtpsif_req_serviced : std_logic;
-- asp - gbwts & sbwts i/f

signal asp2gbwts_sbwts_available_bytes : std_logic_vector(14 downto 0);


-- update_reqmat - reqmat_arb i/f

signal updatereqmat2reqmatarb_cs : std_logic;

signal updatereqmat2reqmatarb_we : std_logic;

signal updatereqmat2reqmatarb_ack : std_logic;

signal updatereqmat2reqmatarb_addr : std_logic_vector(allocID_width_con - 1 downto 0);

signal updatereqmat2reqmatarb_data : std_logic_vector(reqmat_mem_width_con - 1 downto 0);


-- bap_arbiter - dbarx i/f

signal dbarx2baparb_cs : std_logic;

signal dbarx2baparb_we : std_logic;

signal baparb2dbarx_ack : std_logic;

signal dbarx2baparb_addr : std_logic_vector(allocID_width_con - 1 downto 0);

signal baparb2dbarx_data : std_logic_vector(47 downto 0);


-- reqmat_arbiter - dbarx i/f

signal dbarx2reqmatarb_cs : std_logic;

signal dbarx2reqmatarb_we : std_logic;

signal reqmatarb2dbarx_ack : std_logic;

signal dbarx2reqmatarb_addr : std_logic_vector(allocID_width_con - 1 downto 0);

signal dbarx2reqmatarb_data : std_logic_vector(reqmat_mem_width_con - 1 downto 0);


-- dbarx - mux_dba i/f

signal dbarx2mux_cs : std_logic;

signal dbarx2mux_we : std_logic;

signal mux2dbarx_ack : std_logic;

signal dbarx2mux_addr : std_logic_vector(5 downto 0);

signal dbarx2mux_data : std_logic_vector(15 downto 0);

signal mux2dbarx_data : std_logic_vector(15 downto 0);

signal dbarx2mux_selection : std_logic;


-- dbarx - afifo_dba i/f

signal dbarx2fifo_data : std_logic_vector(19 downto 0);

signal fifo2dbarx_data : std_logic_vector(19 downto 0);

signal fifo2dbarx_empty : std_logic;

signal fifo2dbarx_rd_ack : std_logic;

signal dbarx2fifo_wr_en : std_logic;

signal dbarx2fifo_rd_en : std_logic;
-- mux_dba - flags_tcont3arb i/f

signal mux2flags3arb_req : std_logic;

signal mux2flags3arb_we : std_logic;

signal flags3arb2mux_ack : std_logic;

signal mux2flags3arb_addr : std_logic_vector(5 downto 0);

signal mux2flags3arb_data : std_logic_vector(15 downto 0);

signal flags3arb2mux_data : std_logic_vector(15 downto 0);
-- mux_dba - flags_tcont3arb i/f

signal mux2flags4arb_req : std_logic;

signal mux2flags4arb_we : std_logic;

signal flags4arb2mux_ack : std_logic;

signal mux2flags4arb_addr : std_logic_vector(5 downto 0);

signal mux2flags4arb_data : std_logic_vector(15 downto 0);

signal flags4arb2mux_data : std_logic_vector(15 downto 0);
-- flags_tcont3arb - flags_tcont3

signal flags3arb2memflags3_addr : std_logic_vector(5 downto 0);

signal flags3arb2memflags3_en : std_logic;

signal flags3arb2memflags3_we : std_logic;

signal flags3arb2memflags3_data : std_logic_vector(15 downto 0);

signal memflags32flags3arb_data : std_logic_vector(15 downto 0);


-- flags_tcont4arb - flags_tcont4

signal flags4arb2memflags4_addr : std_logic_vector(5 downto 0);

signal flags4arb2memflags4_en : std_logic;

signal flags4arb2memflags4_we : std_logic;

signal flags4arb2memflags4_data : std_logic_vector(15 downto 0);

signal memflags42flags4arb_data : std_logic_vector(15 downto 0);


-- sbwti - flags_tcont3arb i/f

signal sbwti2flags3arb_addr : std_logic_vector(5 downto 0);

signal sbwti2flags3arb_we : std_logic;

signal sbwti2flags3arb_req : std_logic;

signal flags3arb2sbwti_ack : std_logic;

signal flags3arb2sbwti_data : std_logic_vector(15 downto 0);

signal sbwti2flags3arb_data : std_logic_vector(15 downto 0);
-- sbwti - flags_tcont3arb i/f

signal sbwti2flags4arb_addr : std_logic_vector(5 downto 0);

signal sbwti2flags4arb_we : std_logic;

signal sbwti2flags4arb_req : std_logic;

signal flags4arb2sbwti_ack : std_logic;

signal flags4arb2sbwti_data : std_logic_vector(15 downto 0);

signal sbwti2flags4arb_data : std_logic_vector(15 downto 0);
-- sbwti - minsdi memA portA

signal sbwti2minsdimema_addra : std_logic_vector(allocID_width_con - 1 downto 0);

signal sbwti2minsdimema_ena : std_logic;

signal sbwti2minsdimema_wea : std_logic;

signal minsdimema2sbwti_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);

signal sbwti2minsdimema_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);


-- sbwti - minsdi memB portA

signal sbwti2minsdimemb_addra : std_logic_vector(allocID_width_con - 1 downto 0);

signal sbwti2minsdimemb_ena : std_logic;

signal minsdimemb2sbwti_dataa : std_logic_vector(SDI_mem_width_con - 1 downto 0);

-- sbwti - sbwts i/f

signal sbwti2sbwts_allocID_valid : std_logic;

signal sbwti2sbwts_allocID : std_logic_vector(allocID_width_con - 1 downto 0);

signal sbwti2sbwts_stall_inspection : std_logic;

signal sbwti2sbwts_flags_inspected : std_logic;
-- sbwts - bap_arbiter & reqmat_arbiter i/f

signal sbwts2baparb_reqmatarb_req : std_logic;

signal sbwts2baparb_reqmatarb_addr : std_logic_vector(allocID_width_con - 1 downto 0);
-- sbwts - bap_arbiter i/f

signal sbwts2baparb_we : std_logic;

signal baparb2sbwts_ack : std_logic;

signal baparb2sbwts_data : std_logic_vector(47 downto 0);


-- sbts - reqmat_arbiter i/f

signal sbwts2reqmatarb_we : std_logic;

signal reqmatarb2sbwts_ack : std_logic;

signal reqmatarb2sbwts_data : std_logic_vector(reqmat_mem_width_con - 1 downto 0);


-- sbwts - asp i/f

signal sbwts2asp_rdy : std_logic;

signal sbwts2asp_allocID : std_logic_vector(allocID_width_con - 1 downto 0);

signal sbwts2asp_onuID : std_logic_vector(7 downto 0);

signal sbwts2asp_alloc_bytes : std_logic_vector(15 downto 0);

signal sbwts2asp_pcbu_fec : std_logic_vector(5 downto 0);


signal fifo_arst : std_logic;
signal updatereqmat2flags3arb_req : std_logic;

signal updatereqmat2flagsarb_req_s : std_logic;

signal flag_selection_s : std_logic;

signal bwmapforwarder2bwmapmux_rd : std_logic;

signal bwmapmux2mwmapforwarder_data : std_logic_vector(71 downto 0);

signal bwmapmux2mwmapforwarder_empty : std_logic;

signal bwmapmux2bwmapfifo1_rd : std_logic;

signal bwmapmux2bwmapfifo1_wr : std_logic;

signal bwmapfifo12bwmapmux_empty : std_logic;

signal bwmapmux2bwmapfifo1_data : std_logic_vector(71 downto 0);

signal bwmapfifo12bwmapmux_data : std_logic_vector(71 downto 0);

signal bwmapmux2bwmapfifo2_rd : std_logic;

signal bwmapmux2bwmapfifo2_wr : std_logic;

signal bwmapfifo22bwmapmux_empty : std_logic;

signal bwmapmux2bwmapfifo2_data : std_logic_vector(71 downto 0);

signal bwmapfifo22bwmapmux_data : std_logic_vector(71 downto 0);


signal crcinsertion2bwmapmux_wr : std_logic;

signal crcinsertion2bwmapmux_data : std_logic_vector(71 downto 0);

signal gxtpsif2bwmapforwarder_req : std_logic;

signal gxtpsif2bwmapforwarder_ID : std_logic_vector(11 downto 0);

signal bwmapforwarder2gxtpsif_req_serviced : std_logic;
signal asp2bwmapmux_selection : std_logic;

signal asp2bwmapforwarder_number : std_logic_vector(13 downto 0);

signal asp2bwmapforwarder_dark_indication : std_logic;

signal asp2bwmapforwarder_spec_included : std_logic;

signal asp2bwmapforwarder_valid : std_logic;

signal bwmapforwarder2asp_allow_SBA : std_logic;

signal bwmapforwarder2asp_allow_SBA_s : std_logic;

signal bwmapforwarder2asp_allocid : std_logic_vector(11 downto 0);

signal bwmapforwarder2asp_PLSu : std_logic;

signal bwmapforwarder2asp_PLOAM : std_logic;

signal bwmapforwarder2asp_FEC : std_logic;

signal bwmapforwarder2asp_valid : std_logic;


signal parbus2meminit_onu_info : std_logic_vector(9 downto 0);

signal parbus2meminit_onu_valid : std_logic;

signal parbus2onuservice_ploam : std_logic_vector(12 downto 0);

signal parbus2bwmapforwarder_ranging_delay : std_logic_vector(15 downto 0);
signal asp2crcinsertion_valid : std_logic;

signal asp2crcinsertion_as : std_logic_vector(71 downto 8);


signal updatereqmat2flags3arb_we : std_logic;

signal flagar2updreq_ack : std_logic;

signal flags3arb2updatereqmat_ack : std_logic;

signal flags4arb2updatereqmat_ack : std_logic;


signal updatereqmat2flags3arb_addr : std_logic_vector(5 downto 0);

signal updatereqmat2flags3arb_data : std_logic_vector(15 downto 0);

signal flags3arb2updatereqmat_data : std_logic_vector(15 downto 0);

signal gbwts2asp_plsu_ploam : std_logic_vector(1 downto 0);

signal sbwts2asp_plsu_ploam : std_logic_vector(1 downto 0);
signal onuservice2ts_PLSu_PLOAM_valid : std_logic;

signal onuservice2ts_PLSu_PLOAM_flags : std_logic_vector(1 downto 0);

signal gxtpsif2bwmapforwarder_PLSu_PLOAM : std_logic_vector(1 downto 0);
signal gbwts2updatereqmat_alloc_bytes : std_logic_vector(15 downto 0);

signal asp2gbwts_trigger : std_logic;

signal gbwts2updatereqmat_cmd : std_logic;

signal gbwts2updatereqmat_t_cont : std_logic_vector(1 downto 0);


signal sbwts2updatereqmat_alloc_bytes : std_logic_vector(15 downto 0);

signal sbwts2updatereqmat_cmd : std_logic;

signal sbwts2updatereqmat_t_cont : std_logic_vector(1 downto 0);

signal sbwtu2minsdimema_addrb : std_logic_vector(9 downto 0);

signal sbwtu2minsdimema_enb : std_logic;

signal sbwtu2minsdimema_web : std_logic;

signal sbwtu2minsdimema_datab : std_logic_vector(SDI_mem_width_con - 1 downto 0);

signal minsdimema2sbwtu_datab: std_logic_vector(SDI_mem_width_con - 1 downto 0);

signal updatereqmat2flags4arb_req:std_logic;

signal flags4arb2updatereqmat_data:std_logic_vector(15 downto 0);


signal asp2sbwts_en :std_logic;

signal gbwti2fifo_we_s :std_logic;

----------------------------------------------------------------------

signal CLK0_W: std_logic;

signal LOCK : std_logic;

signal frame_number :std_logic_vector(15 downto 0);

signal gbwts2updatereqmat_req_data_in: std_logic_vector(20 downto 0);

signal sbwts2updatereqmat_req_data_in: std_logic_vector(20 downto 0);

signal sbwtu2sbwti_SDItimers_updated : std_logic;
signal MAC_sft_reset : std_logic;

signal allow_dba : std_logic;

signal rstn_s : std_logic;

signal MAC_control_unused:std_logic_vector(2 downto 0);

signal asp2sbwts_en_s:std_logic;

-----------------------------------

begin

----------------------------------------------------------------------



--------------------- DCM INSTANTIATION ------------------------------

----------------------------------------------------------------------

U_DCM : DCM

port map (CLKIN => gxtp_clk,

CLKFB => clk,

DSSEN => zeros1,

PSINCDEC => zeros1,

PSEN => zeros1,

PSCLK => zeros1,

RST => zeros1,

CLK0 => CLK0_W,

LOCKED => LOCK

);
----------------------------------------------------------------------

-------------- BUFG INSTANTIATION ------------------------------------

----------------------------------------------------------------------

U_BUFG : BUFG

port map (I => CLK0_W,

O => clk


);
----------------------------------------------------------------------

-- SPI2PARALLEL = SERIAL TO PARALLEL & INTERFACE WITH OBC ----------

----------------------------------------------------------------------

spi_inst : spi2parallel

port map(

clk => clk,

rstn => rstn_s,

--SPI Motorola i/f

spi_clk => spi_clk,

MAC_mosi => MAC_mosi,

MAC_miso => MAC_miso,

MAC_cs => MAC_cs,

--Parallel bus i/f

par_cs => spi2parbus_cs,

par_we => spi2parbus_we,

par_addr => spi2parbus_addr,

par_data => spi2parbus_data,

par2spi_addr => parbus2spi_addr,

par2spi_data => parbus2spi_data

);
----------------------------------------------------------------------

----- PARALLEL_BUS = PARALLEL BUS & AGGREGATION OF ALL PARAMETERS --

----------------------------------------------------------------------

par_bus_inst: parallel_bus

generic map(

allocID_gen => allocID_width_con,

TB_gen => TB_width_con,

SDI_gen => SDI_width_con

)
port map(

clk => clk,

rstn => rstn,


--SPI2Par i/f

cs => spi2parbus_cs,

we => spi2parbus_we,

addr => spi2parbus_addr,

din => spi2parbus_data,

dout => parbus2spi_data,

addr2spipar => parbus2spi_addr,
--mem_initializer i/f

allocID_valid => parbus2meminit_allocID_valid,

allocID => parbus2meminit_allocID,

MaxTB => parbus2meminit_MaxTB,

MinTB => parbus2meminit_MinTB,

MaxSDI => parbus2meminit_MaxSDI,

MinSDI => parbus2meminit_MinSDI,

ResONU => parbus2meminit_ResONU,

--mem_init i/f

ONU_info => parbus2meminit_onu_info,

ONU_valid => parbus2meminit_onu_valid,
--onu_service i/f

PLOAMint => parbus2onuservice_ploam,

--to various entities

MAC_control (4) =>MAC_sft_reset,

MAC_control (3) =>allow_dba,

MAC_control (2 downto 0) => MAC_control_unused,


--bwmap_forwarder i/f

Ranging_delay => parbus2bwmapforwarder_ranging_delay--,


);
----------------------------------------------------------------------

----- MEM_INITIALIZER = MEMORIES INITIALIZER (BAP, SDIs, ...)-------

----------------------------------------------------------------------

mem_init_inst : mem_initializer

generic map(

allocID_gen => allocID_width_con,

TB_gen => TB_width_con,

SDI_gen => SDI_width_con,

sdi_mem_gen => sdi_mem_width_con

)
port map(

clk => clk,

rstn => rstn_s,


--Parallel bus i/f

AllocID_valid => parbus2meminit_allocID_valid,

AllocId => parbus2meminit_allocID,

maxTB => parbus2meminit_MaxTB,

minTB => parbus2meminit_MinTB,

maxSDI => parbus2meminit_MaxSDI,

minSDI => parbus2meminit_MinSDI,

resONU => parbus2meminit_ResONU,

frame_duration => "10010111111000" , --frame_duration => parbus2meminit_Frame_Duration,

ONU_info => parbus2meminit_onu_info,

ONU_valid => parbus2meminit_onu_valid,

--memB port b i/f

sbw_memb_addrb => meminit2minsdimemb_addrb,

sbw_memb_dinb => meminit2minsdimemb_datab,

sbw_memb_enb => meminit2minsdimemb_enb,

sbw_memb_web => meminit2minsdimemb_web,

-- sbw ti i/f

sbwti_addr => sbwti2minsdimemb_addra,

--bap_arbiter i/f

bap_en => meminit2baparb_en,

bap_we => meminit2baparb_we,

bap_addr => meminit2baparb_addr,

bap_douta => baparb2meminit_data,
--ONU service i/f

active_ONUs_ID => meminit2onuservice_active_ONUids,

FEC_enabled_ONUs => meminit2bwmapforwarder_FEC_v,

--to all other components

frame_number =>frame_number , -- :out std_logic_vector(15 downto 0);

fclk => fclk_s

);
----------------------------------------------------------------------

----- MAXSDI_MEM timers (these are updated every frame)---------

----------------------------------------------------------------------

--MAX SDI TIMERS

maxsdi_a: max_sdi_mem

port map (

clk => clk,

en => gbwti2maxsdimema_ena,

we => gbwti2maxsdimema_wea,

addr=> gbwti2maxsdimema_addra,

din => gbwti2maxsdimema_dataa,

dout=> maxsdimema2gbwti_dataa

);

-------------------------------------------------------------------------------



----- MAXSDI_MEM parameters (this is written only when a new allocId is ------

----- activated) ---------

-------------------------------------------------------------------------------

--MAX SDI TIMERS

maxsdi_b: max_sdi_mem

port map (

clk => clk,

en => gbwti2maxsdimemb_ena,

we => gbwti2maxsdimemb_wea,

addr=> gbwti2maxsdimemb_addra,

din => gbwti2maxsdimemb_dataa,

dout=> maxsdimemb2gbwti_dataa

);

----------------------------------------------------------------------



----- GBWTI = TIMER INSPECTION LOGIC FROM SDIs ---------------------

----------------------------------------------------------------------

gbwti_inst : gbw_ti

generic map(


allocid_gen => allocid_width_con,

SDI_gen => SDI_width_con,

sdi_mem_gen => sdi_mem_width_con
)
port map(

rstn => rstn_s,

clk => clk,

fclk => gbwts2asp_gbwti_assigned,


--Parallel bus i/f

AllocID_valid => parbus2meminit_allocID_valid,

AllocId => parbus2meminit_allocID,

maxSDI => parbus2meminit_MaxSDI,


--maxsdi i/f a

mema_addr => gbwti2maxsdimema_addra,

mema_en => gbwti2maxsdimema_ena,

mema_we => gbwti2maxsdimema_wea,

mema_din => maxsdimema2gbwti_dataa,

mema_dout => gbwti2maxsdimema_dataa,


--maxsdi i/f b

memb_addr => gbwti2maxsdimemb_addra,

memb_en => gbwti2maxsdimemb_ena,

memb_we => gbwti2maxsdimemb_wea,

memb_din => maxsdimemb2gbwti_dataa,

memb_dout => gbwti2maxsdimemb_dataa,


--afifo i/f

fifo_dout => gbwti2fifo_data,

fifo_we => gbwti2fifo_we --,
);
----------------------------------------------------------------------

----- AFIFO = FIFO FOR STORING THE ALLOCIDs INSPECTED BY "TI" ------

----------------------------------------------------------------------

fifo_1_inst: afifo_maxsdi

port map(

ainit => fifo_arst,


wr_clk => clk,

din => gbwti2fifo_data,

wr_en => gbwti2fifo_we_s,

full => open,

wr_ack => open,
rd_clk => clk,

rd_en => gbwts2afifo_fetch,

dout => afifo2gbwts_allocID,

empty => afifo2gbwts_inspection_completed,

rd_ack => afifo2gbwts_valid

);
----------------------------------------------------------------------

----- GBWTS = GUARANTEED BANDWIDTH TIMER SERVICE -------------------

----------------------------------------------------------------------

gbwts_inst:gbw_ts

port map(

clk => clk,

rstn => rstn_s,

fclk => asp2gbwts_trigger, ---fclk_s,

--afifo_maxsdi i/f

allocID_fetch => gbwts2afifo_fetch,

allocID_valid => afifo2gbwts_valid,

allocID => afifo2gbwts_allocID,

fifo_empty => afifo2gbwts_inspection_completed,


--bap & reqmat access

mem_req => gbwts2baparb_reqmatarb_req,

mem_addr => gbwts2baparb_reqmatarb_addr,
--bap i/f

bap_we => gbwts2baparb_we,

bap_valid => baparb2gbwts_valid,

bap_param => baparb2gbwts_data,


--reqmat i/f

reqmat_we => gbwts2reqmatarb_we,

reqmat_valid => gbwts2reqmatarb_valid,

reqmat_param => reqmatarb2gbwts_data,


--ONU_service i/f

ONU_service_req => gbwts2onuservice_req,

PLSu_PLOAM_valid => onuservice2ts_PLSu_PLOAM_valid,

PLSu_PLOAM_flags => onuservice2ts_PLSu_PLOAM_flags,

------ to update reqmat ----------------------------

allocation_bytes =>gbwts2updatereqmat_alloc_bytes, ---:out std_logic_vector(15 downto 0);

update_reqmat_cmd =>gbwts2updatereqmat_cmd,

request => gbwts2updatereqmat_req_data_in, --:out std_logic_vector(20 downto 0);

t_cont (1 downto 0) =>gbwts2updatereqmat_t_cont,

--asp i/f

available_bytes => asp2gbwts_sbwts_available_bytes,

GBWstruct_RDY => gbwts2asp_rdy,

GBWstruct_allocid => gbwts2asp_allocid,

GBWonu_id => gbwts2asp_onuid,

GBWplsu_PLOAM => gbwts2asp_plsu_ploam,

GBWalloc_bytes => gbwts2asp_alloc_bytes,

GBWpcbu_fec => gbwts2asp_pcbu_fec,

GBW_assigned => gbwts2asp_gbwti_assigned

);
----------------------------------------------------------------------

----- REQMAT_ARBITER = REQUEST MATRIX ARBITER ----------------------

----------------------------------------------------------------------

reqmat_arb_inst : arbiter

generic map(

addr_gen => allocid_width_con,

mem_width_gen => reqmat_mem_width_con

)
port map(

clk => clk,

rstn => rstn_s,


--gbwts i/f

A_addr => gbwts2baparb_reqmatarb_addr,

A_we => gbwts2reqmatarb_we,

A_req => gbwts2baparb_reqmatarb_req,

A_ack => gbwts2reqmatarb_valid,

A_din => zeros21,

A_dout => reqmatarb2gbwts_data,
--sbwts i/f

B_addr => sbwts2baparb_reqmatarb_addr,

B_we => sbwts2reqmatarb_we,

B_req => sbwts2baparb_reqmatarb_req,

B_ack => reqmatarb2sbwts_ack,

B_din => zeros21,

B_dout => reqmatarb2sbwts_data,
--update_reqmat i/f

C_addr => updatereqmat2reqmatarb_addr,

C_we => updatereqmat2reqmatarb_we,

C_req => updatereqmat2reqmatarb_cs,

C_ack => updatereqmat2reqmatarb_ack,

C_din => updatereqmat2reqmatarb_data,

C_dout => open, --reqmatarb2updatereqmat_data,
--dba_Rx i/f

D_addr => dbarx2reqmatarb_addr,

D_we => dbarx2reqmatarb_we,

D_req => dbarx2reqmatarb_cs,

D_ack => reqmatarb2dbarx_ack,

D_din => dbarx2reqmatarb_data, --non-linear coding is written by dba_rx

D_dout => open,

--memory i/f

mem_addr => reqmatarb2reqmatmem_addr,

mem_en => reqmatarb2reqmatmem_en,

mem_we => reqmatarb2reqmatmem_we,

mem_dout => reqmatarb2reqmatmem_data,

mem_din => reqmatmem2reqmatarb_data

);
----------------------------------------------------------------------

----- BAP_ARBITER = BANDWIDTH ALLOCATION PARAMETERS ARBITER --------

----------------------------------------------------------------------

bap_arb_inst : arbiter

generic map(

addr_gen => allocid_width_con,

mem_width_gen => bap_mem_width_con

)
port map(

clk => clk,

rstn => rstn_s,
--gbwts i/f

A_addr => gbwts2baparb_reqmatarb_addr,

A_we => gbwts2baparb_we,

A_req => gbwts2baparb_reqmatarb_req,

A_ack => baparb2gbwts_valid,

A_din => zeros48,

A_dout => baparb2gbwts_data,
--sbwts i/f

B_addr => sbwts2baparb_reqmatarb_addr,

B_we => sbwts2baparb_we,

B_req => sbwts2baparb_reqmatarb_req,

B_ack => baparb2sbwts_ack,

B_din => zeros48,

B_dout => baparb2sbwts_data,
--dba_Rx i/f

C_addr => dbarx2baparb_addr,

C_we => dbarx2baparb_we,

C_req => dbarx2baparb_cs,

C_ack => baparb2dbarx_ack,

C_din => zeros48, --2BE DEFINED 1 downto 0

C_dout => baparb2dbarx_data,
--mem init

D_addr => meminit2baparb_addr,

D_we => meminit2baparb_we,

D_req => meminit2baparb_en,

D_ack => open, --baparb2meminit_ack,

D_din => baparb2meminit_data,

D_dout => open, --meminit2baparb_data,

--memory i/f

mem_addr => baparb2bapmem_addr,

mem_en => baparb2bapmem_en,

mem_we => baparb2bapmem_we,

mem_dout => baparb2bapmem_data,

mem_din => bapmem2baparb_data

);
----------------------------------------------------------------------

----- BAP_MEM = BANDWIDTH ALLOCATION PARAMETERS MEMORY -------------

----------------------------------------------------------------------

bap_mem_inst: bap_mem

port map(

addr => baparb2bapmem_addr,

clk => clk,

din => baparb2bapmem_data,

dout => bapmem2baparb_data,

en => baparb2bapmem_en,

nd => zeros1,

rfd => open,

rdy => open, --bapmem2baparb_rdy,

we => baparb2bapmem_we

);
----------------------------------------------------------------------

----- REQMAT_MEM = REQUEST MATRIX MEMORY ---------------------------

----------------------------------------------------------------------

reqmat_inst : reqmat_mem

port map(

addr => reqmatarb2reqmatmem_addr,

clk => clk,

din => reqmatarb2reqmatmem_data,

dout => reqmatmem2reqmatarb_data,

en => reqmatarb2reqmatmem_en,

nd => zeros1,

rfd => open,

rdy => open,

we => reqmatarb2reqmatmem_we

);
----------------------------------------------------------------------

----- ONU_SERVICE ----------------------------------------------------

----------------------------------------------------------------------

onu_service_inst: onu_service

port map(

clk => clk,

rstn => rstn_s,

fclk => fclk_s,
--ts i/f

plsu_ploam_req => ts2onuservice_req,

ONUID => ts2onuservice_onuid,
--gbwts & sbwts i/f

plsu_ploam_valid => onuservice2ts_PLSu_PLOAM_valid,

plsu_ploam => onuservice2ts_PLSu_PLOAM_flags,

--asp i/f

pending_urgent_PLOAM_req => onuservice2asp_urgent_PLOAM_req,

ONU_service_struct_valid => onuservice2asp_struct_valid,

ONU_service_struct_allocID => onuservice2asp_struct_allocID,

ONU_service_ONU_id => onuservice2asp_ONU_id,

ONU_service_alloc_bytes => onuservice2asp_alloc_bytes,

ONU_service_pcbu_fec => onuservice2asp_pcbu_fec,

ONU_service_assigned => onuservice2asp_assigned,
--mem_initializer i/f

active_ONUs => meminit2onuservice_active_ONUids,

FEC_v => meminit2bwmapforwarder_FEC_v,

-- parallel bus i/f

PLOAM_interval => parbus2onuservice_ploam(12 downto 1),

Regular_PLOAM_mechanism_enable => parbus2onuservice_ploam(0),

-------- GXTP SIF

GXTP_SIF_onuid => gxtpsif2onuservice_onuid,

Explicit_PLOAM_req => gxtpsif2onuservice_explicit_ploam_req,

Explicit_PLSu_req => gxtpsif2onuservice_explicit_plsu_req,

GXTP_SIF_req_serviced => onuservice2gxtpsif_req_serviced

);
----------------------------------------------------------------------

----- GXTP_SIF = GXTP SERIAL INTERFACE -----------------------------

----------------------------------------------------------------------

gxtp_sif_inst: gxtp_sif

port map(

clk => clk,

rstn => rstn_s,


--GXTP SIF signal

-- GXTP_sif_clk => GXTP_sif_clk,

GXTP_sif_data => GXTP_sif_data,
--to whom it may concern

GXTP_ranging_request => gxtpsif2bwmapforwarder_req,

GXTP_ranging_ID => gxtpsif2bwmapforwarder_ID,

GXTP_ranging_PLSu_PLOAM =>gxtpsif2bwmapforwarder_PLSu_PLOAM, ----:out std_logic_vector(1 downto 0);

GXTP_ranging_request_service => bwmapforwarder2gxtpsif_req_serviced,
--ONU_service interface

GXTP_SIF_onuid => gxtpsif2onuservice_onuid,

Explicit_PLOAM_req => gxtpsif2onuservice_explicit_ploam_req,

Explicit_PLSu_req => gxtpsif2onuservice_explicit_plsu_req,

GXTP_SIF_req_serviced => onuservice2GXTPSIF_req_serviced

);
----------------------------------------------------------------------

----- ASP = ACCESS STRUCTURE PREPARATION UNIT ----------------------

----------------------------------------------------------------------

asp_inst: asp

port map(

clk => clk,

rstn => rstn_s,

fclk => fclk_s,
--gbwts i/f

GBWstruct_valid => gbwts2asp_rdy,

GBWstruct_allocid => gbwts2asp_allocid,

GBWonu_id => gbwts2asp_onuid,

GBWalloc_bytes => gbwts2asp_alloc_bytes,

GBWpcbu_fec => gbwts2asp_pcbu_fec,

GBWplsu_ploam => gbwts2asp_plsu_ploam,

GBW_assigned => gbwts2asp_gbwti_assigned,

GBW_ts_en => asp2gbwts_trigger, --open,

--sbwts i/f

SBWstruct_valid => sbwts2asp_rdy,

SBWstruct_allocid => sbwts2asp_allocid,

SBWonu_id => sbwts2asp_onuid,

SBWalloc_bytes => sbwts2asp_alloc_bytes,

SBWpcbu_fec => sbwts2asp_pcbu_fec,

SBWplsu_ploam => sbwts2asp_plsu_ploam,

SBW_ts_en => asp2sbwts_en, --open,
--gbwts & sbwts i/f

available_bytes => asp2gbwts_sbwts_available_bytes,


--onu_service i/f

ONU_po_struct_valid => onuservice2asp_struct_valid,

ONU_po_struct_allocID => onuservice2asp_struct_allocID,

ONU_po_ONU_id => onuservice2asp_ONU_id,

ONU_po_alloc_bytes => onuservice2asp_alloc_bytes,

ONU_po_pcbu_fec => onuservice2asp_pcbu_fec,

ONU_po_plsu_ploam => onuservice2ts_PLSu_PLOAM_flags, --onuservice2asp_plsu_ploam,

ONU_po_assigned => onuservice2asp_assigned,

ONU_po_en => onuservice2asp_urgent_PLOAM_req,

--bwmap_forwarder i/f

BWmap_header(13 downto 0) => asp2bwmapforwarder_number,

BWmap_header(14) => asp2bwmapforwarder_dark_indication,

BWmap_header(15) => asp2bwmapforwarder_spec_included,

BWmap_header_valid => asp2bwmapforwarder_valid,

allow_SBA => bwmapforwarder2asp_allow_SBA,

Spec_broad_req_allocid => bwmapforwarder2asp_allocid,

Spec_broad_req_FEC => bwmapforwarder2asp_FEC,

Spec_broad_req_PLSu => bwmapforwarder2asp_PLSu,

Spec_broad_req_PLOAM => bwmapforwarder2asp_PLOAM,

Spec_broad_req_valid => bwmapforwarder2asp_valid,

--crc insertion

BWmap_fifo_selection => asp2bwmapmux_selection,

access_structure_valid => asp2crcinsertion_valid,

access_structure => asp2crcinsertion_as --access structure

);

---------------------------------------------------------------



----- UPDATE_REQMAT = UNIT FOR UPDATING THE REQUEST MATRIX --

---------------------------------------------------------------

update_reqmat_inst : update_reqmat

port map(

clk => clk,

rstn => rstn_s,

--gbwts i/f

gbw_valid => gbwts2updatereqmat_cmd, --from gbwts when T-CONt is 1

gbw_allocID => gbwts2asp_allocid, --from gbwts to asp & update_reqmat

gbw_allocation_bytes => gbwts2updatereqmat_alloc_bytes , --from gbwts to update_reqmat

gbw_req_data_in => gbwts2updatereqmat_req_data_in, ----- : in std_logic_vector(20 downto 0);

gbw_tcont(2) =>'0',

gbw_tcont(1 downto 0) => gbwts2updatereqmat_t_cont, --

--sbwts i/f

sbw_valid => sbwts2updatereqmat_cmd,

sbw_allocID => sbwts2asp_allocid,

sbw_allocation_bytes => sbwts2updatereqmat_alloc_bytes ,

sbw_req_data_in => sbwts2updatereqmat_req_data_in, ----- : in std_logic_vector(20 downto 0);

sbw_tcont(2) => '0',

sbw_tcont(1 downto 0) => sbwts2updatereqmat_t_cont,

--reqmat i/f

req_cs => updatereqmat2reqmatarb_cs,

req_we => updatereqmat2reqmatarb_we,

req_ack => updatereqmat2reqmatarb_ack,

req_addr => updatereqmat2reqmatarb_addr,

req_data_out => updatereqmat2reqmatarb_data,


---- dba_rx i/f

dbarx_flag_selection => dbarx2mux_selection, -- : in std_logic;

dbarx_flag_addr => dbarx2mux_addr, -- : in std_logic_vector(5 downto 0);

--tcont3/tc

flag_cs => updatereqmat2flagsarb_req_s,

flag_we => updatereqmat2flags3arb_we,

flag_ack => flagar2updreq_ack,

flag_selection => flag_selection_s,

flag_addr => updatereqmat2flags3arb_addr,

flag_data_out => updatereqmat2flags3arb_data,

flag3_data_in => flags3arb2updatereqmat_data,

flag4_data_in =>flags4arb2updatereqmat_data

);

---------------------------------------------------------------



----- DBA REPORT RECEIVER; INTERFACE WITH GXTP ----------------

---------------------------------------------------------------

dba_rx_inst : dba_rx

port map(

clk => clk,

rstn => rstn_s,


--gxtp i/f

dba_valid => dba_valid,

dba_bus => dba_bus,
--bap i/f

bap_cs => dbarx2baparb_cs,

bap_we => dbarx2baparb_we,

bap_ack => baparb2dbarx_ack,

bap_addr => dbarx2baparb_addr,

bap_data => baparb2dbarx_data,


--reqmat i/f

reqmat_req => dbarx2reqmatarb_cs,

reqmat_we => dbarx2reqmatarb_we,

reqmat_ack => reqmatarb2dbarx_ack,

reqmat_addr => dbarx2reqmatarb_addr,

reqmat_data => dbarx2reqmatarb_data,

-- update_reqmat i/f ---------

update_reqmat_addr =>updatereqmat2flags3arb_addr , --: in std_logic_vector(5 downto 0);

update_reqmat_selection => flag_selection_s,

--flags i/f via mux

flag_cs => dbarx2mux_cs,

flag_we => dbarx2mux_we,

flag_ack => mux2dbarx_ack,

flag_selection=> dbarx2mux_selection,

flag_addr => dbarx2mux_addr,

flag_data_out => dbarx2mux_data,

flag_data_in => mux2dbarx_data,
--fifo i/f

fifo_dout => dbarx2fifo_data,

fifo_din => fifo2dbarx_data,

fifo_empty => fifo2dbarx_empty,

fifo_wr_en => dbarx2fifo_wr_en,

fifo_rd_en => dbarx2fifo_rd_en,

fifo_rd_ack => fifo2dbarx_rd_ack

);
----------------------------------------------------------------------

----- AFIFO_DBA = FIFO USED TO STORE IN DBA REPORT Rx --------------

----------------------------------------------------------------------

afifo_inst : afifo_dba

port map(

din => dbarx2fifo_data,

wr_en => dbarx2fifo_wr_en,

wr_clk => clk,

rd_en => dbarx2fifo_rd_en,

rd_clk => clk,

ainit => fifo_arst,

dout => fifo2dbarx_data,

full => open,

empty => fifo2dbarx_empty,

rd_ack => fifo2dbarx_rd_ack,

wr_ack => open

);

----------------------------------------------------------------------



----- MUX_DBA = MUX FOR DBA TO SELECT EITHER FLAGS3 OR FLAGS4 ------

----------------------------------------------------------------------

dba_mux_inst : mux_dba

port map(


--dba_rx i/f

cs => dbarx2mux_cs,

we => dbarx2mux_we,

ack => mux2dbarx_ack,

addr => dbarx2mux_addr,

data_to_flags => dbarx2mux_data,

data_from_flags => mux2dbarx_data,

selection => dbarx2mux_selection, --'0' for tcont3 region

--'1' for tcont4 region

--tcont3_flags region i/f via arbiter

cs_flags3 => mux2flags3arb_req,

we_flags3 => mux2flags3arb_we,

ack_flags3 => flags3arb2mux_ack,

addr_flags3 => mux2flags3arb_addr,

data_to_flags3 => mux2flags3arb_data,

data_from_flags3 => flags3arb2mux_data,

--tcont4_flags region i/f via arbiter

cs_flags4 => mux2flags4arb_req,

we_flags4 => mux2flags4arb_we,

ack_flags4 => flags4arb2mux_ack,

addr_flags4 => mux2flags4arb_addr,

data_to_flags4 => mux2flags4arb_data,

data_from_flags4 => flags4arb2mux_data

);


---------------------------------------------------------------

----- ARBITER FOR FLAGS REGION FOR TCONT 3 --------------------

---------------------------------------------------------------

flag3_arb_inst : arbiter

generic map(

addr_gen => flags_width_con,

mem_width_gen => flags_mem_width_con

)
port map(

clk => clk,

rstn => rstn_s,


--from sbwti i/f

A_addr => sbwti2flags3arb_addr,

A_we => sbwti2flags3arb_we,

A_req => sbwti2flags3arb_req,

A_ack => flags3arb2sbwti_ack,

A_din => sbwti2flags3arb_data, --2 BE CHECKED --data input, when sb wants to write the memory

A_dout => flags3arb2sbwti_data, --
-- not needed

B_addr => zeros6,

B_we => '0',

B_req => '0',

B_ack => open,

B_din => zeros16, --data input, when sb wants to write the memory

B_dout => open,
--from dba_Rx i/f

C_addr => updatereqmat2flags3arb_addr,

C_we => updatereqmat2flags3arb_we,

C_req => updatereqmat2flags3arb_req,

C_ack => flags3arb2updatereqmat_ack,

C_din => updatereqmat2flags3arb_data, --data input, when sb wants to write the memory

C_dout => flags3arb2updatereqmat_data,
--update reqmat i/f

D_addr => mux2flags3arb_addr,

D_we => mux2flags3arb_we,

D_req => mux2flags3arb_req,

D_ack => flags3arb2mux_ack,

D_din => mux2flags3arb_data,

D_dout => flags3arb2mux_data,
--memory i/f

mem_addr => flags3arb2memflags3_addr,

mem_en => flags3arb2memflags3_en,

mem_we => flags3arb2memflags3_we,

mem_dout => flags3arb2memflags3_data,

mem_din => memflags32flags3arb_data

);
---------------------------------------------------------------

----- ARBITER FOR FLAGS REGION FOR TCONT 4 --------------------

---------------------------------------------------------------

flag4_arb_inst : arbiter

generic map(

addr_gen => flags_width_con,

mem_width_gen => flags_mem_width_con

)
port map(

clk => clk,

rstn => rstn_s,


--from sbwti i/f

A_addr => sbwti2flags4arb_addr,

A_we => sbwti2flags4arb_we,

A_req => sbwti2flags4arb_req,

A_ack => flags4arb2sbwti_ack,

A_din => sbwti2flags4arb_data, --data input, when sb wants to write the memory

A_dout => flags4arb2sbwti_data,
-- not needed

B_addr => zeros6,

B_we => '0',

B_req => '0',

B_ack => open,

B_din => zeros16, --data input, when sb wants to write the memory

B_dout => open,
--from dba_Rx i/f

C_addr => mux2flags4arb_addr,

C_we => mux2flags4arb_we,

C_req => mux2flags4arb_req,

C_ack => flags4arb2mux_ack,

C_din => mux2flags4arb_data, --data input, when sb wants to write the memory

C_dout => flags4arb2mux_data,
--open ports

D_addr => updatereqmat2flags3arb_addr,

D_we => updatereqmat2flags3arb_we,

D_req => updatereqmat2flags4arb_req,

D_ack => flags4arb2updatereqmat_ack,

D_din => updatereqmat2flags3arb_data,

D_dout => flags4arb2updatereqmat_data,
--memory i/f

mem_addr => flags4arb2memflags4_addr,

mem_en => flags4arb2memflags4_en,

mem_we => flags4arb2memflags4_we,

mem_dout => flags4arb2memflags4_data,

mem_din => memflags42flags4arb_data

);
---------------------------------------------------------------

----- FLAGS REGION FOR TCONT 3 --------------------------------

---------------------------------------------------------------

flags3_inst: flags_mem

port map (

addr=> flags3arb2memflags3_addr,

clk => clk,

din => flags3arb2memflags3_data,

dout => memflags32flags3arb_data,

en => flags3arb2memflags3_en,

we => flags3arb2memflags3_we);

---------------------------------------------------------------

----- FLAGS REGION FOR TCONT 4 --------------------------------

---------------------------------------------------------------

flags4_inst: flags_mem

port map (

addr=> flags4arb2memflags4_addr,

clk => clk,

din => flags4arb2memflags4_data,

dout => memflags42flags4arb_data,

en => flags4arb2memflags4_en,

we => flags4arb2memflags4_we);


----------------------------------------------------------------------

----- SBWTI = SURPLUS BANDWIDTH TIMER INSPECTION IN FLAGS REGION ---

----- AS WELL AS IN MIN SDI TIMERS -----------------------------------

----------------------------------------------------------------------

sbwti_inst : sbw_ti

port map(

clk => clk,

rstn => rstn_s,

fclk =>asp2sbwts_en_s, -- fclk_s, --gbw2sbw_finished, --this is sth like trigger from asp to the sbw part of the fpga

--tcont3_flags i/f

tcont3_we => sbwti2flags3arb_we,

tcont3_en => sbwti2flags3arb_req,

tcont3_addr => sbwti2flags3arb_addr,

tcont3_din => flags3arb2sbwti_data,

tcont3_dout => sbwti2flags3arb_data,

tcont3_rdy => flags3arb2sbwti_ack,

--tcont4_flags i/f

tcont4_we => sbwti2flags4arb_we,

tcont4_en => sbwti2flags4arb_req,

tcont4_addr => sbwti2flags4arb_addr,

tcont4_din => flags4arb2sbwti_data,

tcont4_dout => sbwti2flags4arb_data,

tcont4_rdy => flags4arb2sbwti_ack,

SDItimers_updated => sbwtu2sbwti_SDItimers_updated,

--minsdi mem a i/f(portA)

mema_addr => sbwti2minsdimema_addra,

mema_en => sbwti2minsdimema_ena,

mema_we => sbwti2minsdimema_wea,

mema_din => minsdimema2sbwti_dataa,

mema_dout => sbwti2minsdimema_dataa,

--minsdi mem b i/f (portA)

memb_addr => sbwti2minsdimemb_addra,

memb_en => sbwti2minsdimemb_ena,

memb_din => minsdimemb2sbwti_dataa,

--sbwts i/f

allocID_valid => sbwti2sbwts_allocID_valid,

allocID => sbwti2sbwts_allocID,

stall_inspection => sbwti2sbwts_stall_inspection,

flags_inspected => sbwti2sbwts_flags_inspected

);
---------------------------------------------------------------

----- SBW_TU ---------------------------------------------------

---------------------------------------------------------------

sbw_tu_inst: sbw_tu

generic map(

allocid_gen => allocID_width_con,

sdi_mem_gen => sdi_mem_width_con

)

port map (



rstn => rstn_s,

clk => clk,

fclk => fclk_s,

--minsdi a port b i/f

mema_addr => sbwtu2minsdimema_addrb,

mema_en => sbwtu2minsdimema_enb,

mema_we => sbwtu2minsdimema_web ,

mema_din => minsdimema2sbwtu_datab,

mema_dout => sbwtu2minsdimema_datab,

memx_scan_fin =>sbwtu2sbwti_SDItimers_updated --: out std_logic

);

----------------------------------------------------------------------



----- min SDI timers (these are decreased every frame if positive) ---

----------------------------------------------------------------------

--MIN SDI TIMERS

minsdi_a: sdi_mem

port map(

addra => sbwti2minsdimema_addra,

addrb => sbwtu2minsdimema_addrb,

clka => clk,

clkb => clk,

dina => sbwti2minsdimema_dataa,

dinb => sbwtu2minsdimema_datab,

douta => minsdimema2sbwti_dataa,

doutb => minsdimema2sbwtu_datab,

ena => sbwti2minsdimema_ena,

enb => sbwtu2minsdimema_enb,

wea => sbwti2minsdimema_wea,

web => sbwtu2minsdimema_web

);


-------------------------------------------------------------------------------

-- min SDI parameters (these are written only when a new AllocIDis activated --

-------------------------------------------------------------------------------

--MIN SDI TIMERS

minsdi_b: sdi_mem

port map(

addra => sbwti2minsdimemb_addra,

addrb => meminit2minsdimemb_addrb,

clka => clk,

clkb => clk,

dina => zeros15,

dinb => meminit2minsdimemb_datab,

douta => minsdimemb2sbwti_dataa,

doutb => open,

ena => sbwti2minsdimemb_ena,

enb => meminit2minsdimemb_enb,

wea => '0', --sbwti2minsdimemb_wea,

web => meminit2minsdimemb_web_s

);
----------------------------------------------------------------------

----- SBWTS = SURPLUS BANDWIDTH TIMER SERVICE ----------------------

----------------------------------------------------------------------

sbwts_inst : sbw_ts

port map(

clk => clk,

rstn => rstn_s,

fclk =>fclk_s,

ts_enable => asp2sbwts_en_s,

--sbwti i/f

allocID_valid => sbwti2sbwts_allocID_valid,

allocID => sbwti2sbwts_allocID,

stall_inspection => sbwti2sbwts_stall_inspection,

inspection_completed => sbwti2sbwts_flags_inspected,


--bap & reqmat arbiter i/f

mem_req => sbwts2baparb_reqmatarb_req,

mem_addr => sbwts2baparb_reqmatarb_addr,
--bap_arbiter i/f

bap_we => sbwts2baparb_we,

bap_valid => baparb2sbwts_ack,

bap_param => baparb2sbwts_data,


--reqmat_arbiter i/f

reqmat_we => sbwts2reqmatarb_we,

reqmat_valid => reqmatarb2sbwts_ack,

reqmat_param => reqmatarb2sbwts_data,


--update_reqmat i/f

allocation_bytes => sbwts2updatereqmat_alloc_bytes ,

update_reqmat_cmd => sbwts2updatereqmat_cmd,

request => sbwts2updatereqmat_req_data_in, --:out std_logic_vector(20 downto 0);

t_cont => sbwts2updatereqmat_t_cont,
--asp i/f

available_bytes => asp2gbwts_sbwts_available_bytes,

SBWstruct_RDY => sbwts2asp_rdy,

SBWstruct_allocid => sbwts2asp_allocid,

SBWonu_id => sbwts2asp_onuid,

SBWalloc_bytes => sbwts2asp_alloc_bytes,

SBWpcbu_fec => sbwts2asp_pcbu_fec,

SBWplsu_PLOAM => sbwts2asp_plsu_ploam --,

);
---------------------------------------------------------------

----- BANDWIDTH MAP IS A FIFO MODULE 1 ------------------------

---------------------------------------------------------------

bwmap1_inst : bwmap_fifo

port map (

din => bwmapmux2bwmapfifo1_data,

wr_en => bwmapmux2bwmapfifo1_wr,

clk => clk,

rd_en => bwmapmux2bwmapfifo1_rd,

sinit =>fifo_arst , --rstn,

dout => bwmapfifo12bwmapmux_data,

full => open,

empty => bwmapfifo12bwmapmux_empty--,

);
---------------------------------------------------------------

----- BANDWIDTH MAP IS A FIFO MODULE 2 ------------------------

---------------------------------------------------------------

bwmap2_inst : bwmap_fifo

port map (

din => bwmapmux2bwmapfifo2_data,

wr_en => bwmapmux2bwmapfifo2_wr,

clk => clk,

rd_en => bwmapmux2bwmapfifo2_rd,

sinit => fifo_arst, -- rstn,

dout => bwmapfifo22bwmapmux_data,

full => open,

empty => bwmapfifo22bwmapmux_empty--,


);
--------------------------------------------------------------

----- BWmap_fifo_mux ------------------------------------------

---------------------------------------------------------------
bwmap_mux_inst : BWmap_fifo_mux

port map(

--asp i/f

BWmap_fifo_selection => asp2bwmapmux_selection,


--CRC_insertion --

BWmap_fifo_wr => crcinsertion2bwmapmux_wr,

BWmap_data2fifo => crcinsertion2bwmapmux_data,
--BW map forwarder

BWmap_fifo_rd => bwmapforwarder2bwmapmux_rd,

BWmap_fifo_data => bwmapmux2mwmapforwarder_data,

BWmap_fifo_empty => bwmapmux2mwmapforwarder_empty,


--BWmap fifo 1 i/f

BWmap_fifo1_rd => bwmapmux2bwmapfifo1_rd,

BWmap_fifo1_wr => bwmapmux2bwmapfifo1_wr,

BWmap_fifo1_empty => bwmapfifo12bwmapmux_empty,

BWmap_data2fifo1 => bwmapmux2bwmapfifo1_data,

BWmap_data2entity1 => bwmapfifo12bwmapmux_data,


--BWmap fifo 2 i/f

BWmap_fifo2_rd => bwmapmux2bwmapfifo2_rd,

BWmap_fifo2_wr => bwmapmux2bwmapfifo2_wr,

BWmap_fifo2_empty => bwmapfifo22bwmapmux_empty,

BWmap_data2fifo2 => bwmapmux2bwmapfifo2_data,

BWmap_data2entity2 => bwmapfifo22bwmapmux_data

);
---------------------------------------------------------------

----- BWmap_forwarder -----------------------------------------

---------------------------------------------------------------
BWmap_forwarder_inst : BWmap_forwarder

port map(

clk => clk ,

rstn => rstn_s,

fclk => fclk_s,

-- parallel_bus i/f ---------

enable_regular_ranging => parbus2bwmapforwarder_ranging_delay(12),

regular_ranging_interval => parbus2bwmapforwarder_ranging_delay(11 downto 0),

ranging_delay => parbus2bwmapforwarder_ranging_delay(15 downto 13),

--- GLTP2 sif ---------------

GXTP_ranging_request => gxtpsif2bwmapforwarder_req,

GXTP_ranging_ID => gxtpsif2bwmapforwarder_ID,

GXTP_ranging_PLSu_PLOAM => gxtpsif2bwmapforwarder_PLSu_PLOAM,

GXTP_ranging_request_service => bwmapforwarder2gxtpsif_req_serviced,

---------- i/f to ASP -------

Access_str_number_valid => asp2bwmapforwarder_valid,

Access_str_number => asp2bwmapforwarder_number,

dark_period_indication => asp2bwmapforwarder_dark_indication,

spec_broad_req_included => asp2bwmapforwarder_spec_included,
allow_SBA => bwmapforwarder2asp_allow_SBA,

Spec_broad_req_as(11 downto 0) => bwmapforwarder2asp_allocid,

Spec_broad_req_as(12) => bwmapforwarder2asp_PLSu,

Spec_broad_req_as(13) => bwmapforwarder2asp_PLOAM,

Spec_broad_req_as(14) => bwmapforwarder2asp_FEC,

spec_broad_request => bwmapforwarder2asp_valid,

FEC_v => meminit2bwmapforwarder_FEC_v,

-- Signals to BW map fifo ---

BWmap_fifo_rd => bwmapforwarder2bwmapmux_rd,

BWmap_fifo_data => bwmapmux2mwmapforwarder_data,

BWmap_fifo_empty => bwmapmux2mwmapforwarder_empty,

-- GLTP2 i/f ----------------

BWmap_valid => BWmap_valid,

BWmap_onuid => BWmap_onuid,

BWmap_data => BWmap_data

);
---------------------------------------------------------------

----- CRC8 ---------------------------------------------------

---------------------------------------------------------------

crc_inst : crc_insertion

port map(

clk => clk,

rstn => rstn_s,


--BWmap fifo mux i/f

BWmap_fifo_wr => crcinsertion2bwmapmux_wr,

BWmap_fifo_data => crcinsertion2bwmapmux_data,

--access structure

access_structure_valid => asp2crcinsertion_valid,

access_structure => asp2crcinsertion_as

);
---------------------------------------------------------------------

----------------- RESET FOR Fifos -----------------------------------

fifo_arst <= not rstn_s;
ts2onuservice_req <= gbwts2onuservice_req;

ts2onuservice_onuid <= gbwts2asp_onuid; --gbwts2onuservice_onuid;


----------------------------------------------------------------------

updatereqmat2flags3arb_req <= updatereqmat2flagsarb_req_s AND NOT(flag_selection_s);

updatereqmat2flags4arb_req <= updatereqmat2flagsarb_req_s AND (flag_selection_s);
flagar2updreq_ack <=(flags3arb2updatereqmat_ack and (not flag_selection_s)) or

(flags4arb2updatereqmat_ack and flag_selection_s) ;

gbwti2fifo_we_s <=gbwti2fifo_we and (not gbwts2afifo_fetch );
meminit2minsdimemb_web_s<= (meminit2minsdimemb_web and (not sbwti2minsdimemb_ena));
asp2sbwts_en_s<=asp2sbwts_en and allow_dba;

rstn_s<=rstn and (not MAC_sft_reset);


BWmap_clk <= clk;
---------------------------------------------------------------------

-------- TEST PINS ASSIGNMENT ----------------------------------------

---------------------------------------------------------------------

test_01_meminit_AllocidValid <= parbus2meminit_allocID_valid;

test_02_asp_as <= asp2crcinsertion_as(63 downto 8); -- <###### spi2parbus_cs

test_03_meminit_BapWe <= meminit2baparb_we;

test_04_asp_AsValid <= asp2crcinsertion_valid;

test_05_asp_GbwStructValid <= gbwts2asp_rdy;

test_06_asp_OnuPoStructValid <= onuservice2asp_struct_valid;

test_07_asp_SbwStructValid <= sbwts2asp_rdy;

test_08_asp_SpecBroadReq <= bwmapforwarder2asp_valid;

test_09_asp_GbwStructAllocID <= gbwts2asp_allocid;

test_10_asp_GbwStructAllocBytes <= gbwts2asp_alloc_bytes;

test_11_gbwti_TimersFifoWe <= gbwti2fifo_we;

test_12_gbwts_AllocidFetch <= gbwts2afifo_fetch;

test_13_gbwts_AllocidValid <= afifo2gbwts_valid;

test_14_gbwts_BapAck <= baparb2gbwts_valid;

test_15_gbwts_BapDataIn <= baparb2gbwts_data;

test_16_onuservice_PLSuPLOAMValid <= onuservice2ts_PLSu_PLOAM_valid;

test_17_onuservice_PLSu_PLOAM <= onuservice2ts_PLSu_PLOAM_flags;

test_18_sbwts_SbwStructAllocid <= sbwts2asp_allocid;

test_19_sbwti_AllocidValid <= sbwti2sbwts_allocID_valid;

test_20_crcinsertion_BwmapFifoWe <= crcinsertion2bwmapmux_wr;

test_21_crcinsertion_FifoSelecetion <= asp2bwmapmux_selection;

test_22_bwmapforwarder_BwmapFifoRd <= bwmapforwarder2bwmapmux_rd;

test_23_frame_number <=frame_number;

---------------------------------------------------------------------

--translate_off


dba_monitoring_p: process(clk)

file dba_monitoring_gnt: text OPEN WRITE_MODE is "C:/modeltech_5.7d/giant_project/output_files/dba_monitoring_gnt.txt";

variable lvar1: line;

variable string1 : string(1 to 3) := " | ";

variable string2 : string(1 to 13) := " Simul.Time: ";

variable AllocID : string(1 to 9) := " AllocID "; --RPM1_Granted ";

variable ReportNum : string(1 to 15) := " has requested "; --RPM2_Granted ";

variable Frame_prompt : string(1 to 16) := " bytes in frame ";

begin
if (clk'event and clk = '1') then

if dbarx2reqmatarb_cs='1' then

write (lvar1, NOW);

write (lvar1, AllocID);

write (lvar1, conv_integer(dbarx2reqmatarb_addr));

write (lvar1, ReportNum );

write (lvar1, conv_integer(dbarx2reqmatarb_data));

write (lvar1, Frame_prompt );

write (lvar1, conv_integer(frame_number));

writeline (dba_monitoring_gnt, lvar1);

end if;

end if;


end process;
asp_monitoring_p: process(clk)

file asp_monitoring_gnt: text OPEN WRITE_MODE is "C:/modeltech_5.7d/giant_project/output_files/asp_output.txt";

variable lvar2: line;

variable Frame_prompt : string(1 to 10) := " In frame ";

variable AllocID : string(1 to 9) := " AllocID ";

variable bytes : string(1 to 13) := " is assigned ";

variable start : string(1 to 25) := " bytes. The start ptr is ";

variable stop : string(1 to 17) := " and the stop is ";

variable PLSu : string(1 to 22) := ". The flags are: PLSu ";

variable PLOAM : string(1 to 9) := "PLOAM is ";

variable FEC : string(1 to 7) := "FEC is ";

variable DBRu : string(1 to 8) := "DBRu is ";

variable PLOu : string(1 to 8) := "PLOu is ";

variable SN : string(1 to 6) := "SN is ";

variable dark : string(1 to 8) := "dark is ";

variable NSR : string(1 to 7) := "NSR is ";

variable wholeDba : string(1 to 12) := "wholeDba is ";

variable keno : string(1 to 2) := " ";

begin

if (clk'event and clk = '1') then



if asp2crcinsertion_valid ='1' then

write (lvar2, NOW);

write (lvar2, keno );

write (lvar2, conv_integer(frame_number ));

write (lvar2, keno );

write (lvar2, conv_integer( asp2crcinsertion_as (63 downto 52)));

write (lvar2, keno );

write (lvar2, conv_integer( asp2crcinsertion_as (23 downto 8))-conv_integer( asp2crcinsertion_as (39 downto 24))+1);

write (lvar2, keno );

write (lvar2, conv_integer( asp2crcinsertion_as (39 downto 24)));

write (lvar2, keno );

write (lvar2, conv_integer( asp2crcinsertion_as (23 downto 8)));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (51));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (50));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (49));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (48 downto 47));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (46));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (45));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (44));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (43));

write (lvar2, keno );

write (lvar2, asp2crcinsertion_as (42));

writeline (asp_monitoring_gnt, lvar2);

end if;


end if;

end process;

--translate_on

end architecture GMAC_OLT_a;


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;
package cons_pkg is
--

constant allocID_width_con : positive := 10;

constant TB_width_con : positive := 16;
--original data width of SDI timers (inserted by the OBC)

constant SDI_width_con : positive := 13;


-- Data width of SDI memory

constant SDI_mem_width_con : positive := 15;

-- Data width of Request Matrix memory

constant reqmat_mem_width_con : positive := 21;


-- Data width of Bandwidth Alloc Parameters memory

constant bap_mem_width_con : positive := 48;

-- Constants related to Flags regions for tcont3 and tcont4

constant flags_width_con : positive := 6;



constant flags_mem_width_con : positive := 16;
end package cons_pkg;

7. Βιβλιογραφία


[Βεν 03]

Ιάκωβος Βενιέρης : Δίκτυα ευρείας ζώνης 2003

[Alca ]

Alcatel : Proposal for further study on APON Standards (G.983.1/G.983.2)

[Allo 01]


Alloptic : Ethernet Passive Optical Networks, The International Engineering Consortium, 2001

[ALOP02]


J. D. Angelopoulos, N. Leligou, Th. Orphanoudakis, G. Pikrammenos : Using a multiple priority reservation MAC to support differentiated services over HFC systems , published in the International Journal on Communication Systems 2002

[BrFl]

Broadlight ,Flexlight : Comparing Gigabit PON Technologies ITU-T G.984 GPON vs. IEEE 802.3ah EPON

[eLUM 00]


eLUMINANT : Asynchronous Transfer Mode (ATM), Passive Optical Networks (PONs), The International Engineering Consortium, 2000

[ITU 04]


ITU Recommendations G.984.1 : Gigabit-capable Passive Optical Networks (GPON): Transmission Convergence Layer specification, 2004

[ITU1 03]


ITU Recommendations G.984.1 : Gigabit-capable Passive Optical Networks (GPON): General characteristics, 2003

[ITU2 03]


ITU Recommendations G.984.1 : Gigabit-capable Passive Optical Networks (GPON): Physical Media Dependent (PMD) layer specification, 2003

[KMP 00]


Glen Kramer, Biswanath Mukherjee, Gerry Pesavento : Ethernet PON (ePON): Design and Analysis of an Optical Access Network, August 2000

[LSP 00]


H.C. Leligou, J.Sifnaios, G.Pikrammenos : Hardware implementation of Multimedia Driven HFC MAC protocol, IEEE MELECON2000 conference, May 2000, Cyprus

[Pesa 01]


Gerry Pesavento : Ethernet Passive Optical Networks EPON, IEEE 802.3 Ethernet in the First Mile Study Group, 2001

[Marc 04]

Marconi : http://www.marconi.com 2004

[ShVa96]


M. Shreedhar, G. Varghese : Efficient Fair Queuing using Deficit Round Robin, IEEE Transactions on Networking, Vol.4, No 3, June 1996

[Web 04]

Webtorials : http://www.webtorials.com 2004




1 1 Τον Ιανουάριο του 2003 τα standard του GPON επικυρώθηκαν από την ITU-T και είναι γνωστά ως ITU-TRecommendations G984.1, G984.2 και G984.3.

1   ...   17   18   19   20   21   22   23   24   25


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