Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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Дата канвертавання24.04.2016
Памер2.32 Mb.
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rstn : in std_logic;

--gbwts i/f

gbw_valid : in std_logic;

gbw_allocID : in std_logic_vector (9 downto 0);

gbw_allocation_bytes : in std_logic_vector (15 downto 0);

gbw_req_data_in : in std_logic_vector(20 downto 0);

gbw_tcont : in std_logic_vector (2 downto 0); --3bits tcont_type

--sbwts i/f

sbw_valid : in std_logic;

sbw_allocID : in std_logic_vector (9 downto 0);

sbw_allocation_bytes : in std_logic_vector (15 downto 0);

sbw_req_data_in : in std_logic_vector(20 downto 0);

sbw_tcont : in std_logic_vector (2 downto 0); --3bits tcont_type

--ReqMat_arb i/f

req_cs : out std_logic;

req_we : out std_logic;

req_ack : in std_logic;

req_addr : out std_logic_vector(9 downto 0); --Idio me tou AllocID

req_data_out : out std_logic_vector(20 downto 0);

---- dba_rx i/f

dbarx_flag_selection : in std_logic;

dbarx_flag_addr : in std_logic_vector(5 downto 0);

--tcont3/tcont4 regions i/f

flag_cs : out std_logic;

flag_we : out std_logic;

flag_ack : in std_logic;

flag_selection : out std_logic;

flag_addr : out std_logic_vector(5 downto 0);

flag_data_out : out std_logic_vector (15 downto 0);

flag3_data_in : in std_logic_vector (15 downto 0);

flag4_data_in : in std_logic_vector (15 downto 0)

);

end component;


----------------------------------------------------------------------

------------ DBA_Rx --------------------------------------------

----------------------------------------------------------------------

component dba_rx is

port (

clk : in std_logic;



rstn : in std_logic;

--GXTP i/f

dba_valid : in std_logic;

dba_bus : in std_logic_vector(11 downto 0);

--bap i/f

bap_cs : out std_logic;

bap_we : out std_logic; --Otan 1 tote Write, otan 0 tote read

bap_ack : in std_logic; --From Arbiter of Bap

bap_addr : out std_logic_vector(9 downto 0);

bap_data : in std_logic_vector(47 downto 0); -- the T-CONT type field

--reqmat i/f

reqmat_req : out std_logic;

reqmat_we : out std_logic;

reqmat_ack : in std_logic;

reqmat_addr : out std_logic_vector(9 downto 0); --Idio me tou AllocID

reqmat_data : out std_logic_vector(20 downto 0); -- Nonlinear coding is used.

-- update_reqmat i/f ---------

update_reqmat_addr : in std_logic_vector(5 downto 0);

update_reqmat_selection : in std_logic;

--tcont3/tcont4 regions i/f

flag_cs : out std_logic;

flag_we : out std_logic;

flag_ack : in std_logic;

flag_selection : out std_logic;

flag_addr : out std_logic_vector(5 downto 0);

flag_data_out : out std_logic_vector (15 downto 0);

flag_data_in : in std_logic_vector (15 downto 0);

--afifo_dba i/f

fifo_dout : out std_logic_vector(19 downto 0);

fifo_din : in std_logic_vector(19 downto 0);

fifo_empty : in std_logic;

fifo_wr_en : out std_logic;

fifo_rd_en : out std_logic;

fifo_rd_ack :in std_logic

);

end component;


----------------------------------------------------------------------

------------ AFIFO_DBA -----------------------------------------------

----------------------------------------------------------------------

component afifo_dba IS

port (

din : IN std_logic_VECTOR(19 downto 0);



wr_en : IN std_logic;

wr_clk: IN std_logic;

rd_en : IN std_logic;

rd_clk: IN std_logic;

ainit : IN std_logic;

dout : OUT std_logic_VECTOR(19 downto 0);

full : OUT std_logic;

empty : OUT std_logic;

rd_ack: OUT std_logic;

wr_ack: OUT std_logic

);

END component;


----------------------------------------------------------------------

------------ MUX_DBA -------------------------------------------------

----------------------------------------------------------------------

component mux_dba is

port(

-- clk : in std_logic;



--dba_report_rx i/f

cs : in std_logic;

we : in std_logic;

ack : out std_logic;

addr : in std_logic_vector(5 downto 0);

data_to_flags : in std_logic_vector (15 downto 0);

data_from_flags : out std_logic_vector (15 downto 0);

selection : in std_logic; --'0' for tcont3 region

--'1' for tcont4 region

--tcont3_flags region i/f

cs_flags3 : out std_logic;

we_flags3 : out std_logic;

ack_flags3 : in std_logic;

addr_flags3 : out std_logic_vector(5 downto 0);

data_to_flags3 : out std_logic_vector(15 downto 0);

data_from_flags3: in std_logic_vector(15 downto 0);

--tcont3_flags region i/f

cs_flags4 : out std_logic;

we_flags4 : out std_logic;

ack_flags4 : in std_logic;

addr_flags4 : out std_logic_vector(5 downto 0);

data_to_flags4 : out std_logic_vector(15 downto 0);

data_from_flags4: in std_logic_vector(15 downto 0)

);

END component;


----------------------------------------------------------------------

------------ FLAGS_TCONT_DPMEM ---------------------------------------

----------------------------------------------------------------------

component flags_mem IS

port (

addr: IN std_logic_VECTOR(5 downto 0);



clk: IN std_logic;

din: IN std_logic_VECTOR(15 downto 0);

dout: OUT std_logic_VECTOR(15 downto 0);

en: IN std_logic;

we: IN std_logic);

END component;

----------------------------------------------------------------------

--------------- SBW_TU ----------------------------------------------

----------------------------------------------------------------------

component sbw_tu is

generic(

allocid_gen : positive := 10;

sdi_mem_gen : positive := 15

);
port(

rstn : in std_logic;

clk : in std_logic;

fclk : in std_logic;

--minsdi i/f a

mema_addr : out std_logic_vector(allocid_gen - 1 downto 0);

mema_en : out std_logic;

mema_we : out std_logic;

mema_din : in std_logic_vector(sdi_mem_gen - 1 downto 0); --input from memory 1

mema_dout : out std_logic_vector(sdi_mem_gen - 1 downto 0) ; --output to memory 1

--bit13 = valid_timer

memx_scan_fin : out std_logic

);

end component;


----------------------------------------------------------------------

------------ SBW_TI --------------------------------------------------

----------------------------------------------------------------------

component sbw_ti is

port(

clk : in std_logic;



rstn : in std_logic;

fclk : in std_logic; --this comes from "asp" entity

--tcont3_flags i/f

tcont3_we : out std_logic;

tcont3_en : out std_logic;

tcont3_addr : out std_logic_vector(5 downto 0);

tcont3_din : in std_logic_vector(15 downto 0);

tcont3_dout : out std_logic_vector(15 downto 0);

tcont3_rdy : in std_logic;

--tcont4_flags i/f

tcont4_we : out std_logic;

tcont4_en : out std_logic;

tcont4_addr : out std_logic_vector(5 downto 0);

tcont4_din : in std_logic_vector(15 downto 0);

tcont4_dout : out std_logic_vector(15 downto 0);

tcont4_rdy : in std_logic;


--- sbw tu i/f

SDItimers_updated: in std_logic;

--minsdi mem a i/f

mema_addr : out std_logic_vector(9 downto 0);

mema_en : out std_logic;

mema_we : out std_logic;

mema_din : in std_logic_vector(14 downto 0); --input from memory 1

mema_dout : out std_logic_vector(14 downto 0); --output to memory 1

--minsdi mem b i/f

memb_addr : out std_logic_vector(9 downto 0);

memb_en : out std_logic;

memb_din : in std_logic_vector(14 downto 0);


--sbw_ts i/f

allocID_valid : out std_logic;

allocID : out std_logic_vector(9 downto 0);

stall_inspection : in std_logic;

flags_inspected : out std_logic

);

end component;


------------------------------------------------------------------------

------------ SBW_TS --------------------------------------------

----------------------------------------------------------------------

component sbw_ts is

port(

clk : IN std_logic;



rstn : IN std_logic;

fclk : IN std_logic;

ts_enable : IN std_logic; --from asp entity
allocID_valid : in std_logic;

allocID : in std_logic_vector(9 downto 0); --allocid from timer_inspection entity

inspection_completed : in std_logic; --inspection_completed

stall_inspection : out std_logic;

--bap & reqmat access

mem_req : out std_logic; --a request to bap_arbiter & reqmat_arbiter in the same time

mem_addr : out std_logic_vector(9 downto 0);
--bap i/f

bap_we : out std_logic;

bap_valid : in std_logic;

bap_param : in std_logic_vector(47 downto 0);


--reqmat i/f

reqmat_we : out std_logic;

reqmat_valid : in std_logic;

reqmat_param : in std_logic_vector(20 downto 0);


------ to update reqmat ----------------------------

allocation_bytes :out std_logic_vector(15 downto 0);

update_reqmat_cmd :out std_logic;

request :out std_logic_vector(20 downto 0);

t_cont :out std_logic_vector(1 downto 0);

--asp i/f

SBWstruct_RDY : out std_logic; --this signal serves as an allocid_valid and as RDY signal

SBWstruct_allocid : out std_logic_vector(9 downto 0);

SBWonu_id : out std_logic_vector(7 downto 0);

SBWalloc_bytes : out std_logic_vector(15 downto 0);

SBWpcbu_fec : out std_logic_vector(5 downto 0);

SBWplsu_PLOAM : out std_logic_vector(1 downto 0);

Available_bytes : in std_logic_vector(14 downto 0) --;

);


end component;
----------------------------------------------------------------------

-------------- BWMAP_FIFO --------------------------------------------

----------------------------------------------------------------------

component bwmap_fifo IS

port (

clk: IN std_logic;



sinit: IN std_logic;

din: IN std_logic_vector(71 downto 0);

wr_en: IN std_logic;

rd_en: IN std_logic;

dout: OUT std_logic_vector(71 downto 0);

full: OUT std_logic;

empty: OUT std_logic);

END component;


----------------------------------------------------------------------

-------------- BWmap_fifo_mux ----------------------------------------

----------------------------------------------------------------------
component BWmap_fifo_mux is

port(


--- CRC_insertion ----------------------------------------

BWmap_fifo_wr :in std_logic;

BWmap_data2fifo :in std_logic_vector(71 downto 0);

--- BW map forwarder ----------------------------

BWmap_fifo_rd : in std_logic;

BWmap_fifo_data : out std_logic_vector(71 downto 0);

BWmap_fifo_empty : out std_logic;
BWmap_fifo_selection :in std_logic;

--BWmap fifo 1 i/f

BWmap_fifo1_rd :out std_logic;

BWmap_fifo1_wr :out std_logic;

BWmap_fifo1_empty :in std_logic;

BWmap_data2fifo1 :out std_logic_vector(71 downto 0);

BWmap_data2entity1 :in std_logic_vector(71 downto 0);
--BWmap fifo 1 i/f

BWmap_fifo2_rd :out std_logic;

BWmap_fifo2_wr :out std_logic;

BWmap_fifo2_empty :in std_logic;

BWmap_data2fifo2 :out std_logic_vector(71 downto 0);

BWmap_data2entity2 :in std_logic_vector(71 downto 0)--;

);

end component;



----------------------------------------------------------------------

-------------- BWmap_forwarder ---------------------------------------

----------------------------------------------------------------------

component BWmap_forwarder is

port (

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

fclk : in std_logic;

-- parallel_bus i/f ---------------------------------------

enable_regular_ranging :in std_logic;

regular_ranging_interval :in std_logic_vector(11 downto 0);

------------- start and enable regular ranging is substituted by enable_regular_ranging and regular_ranging_interval

------------- the latter is the programmed value and a timer equal to this is maintained. When it expires,

--------------- ranging has to be performed.

ranging_delay :in std_logic_vector(2 downto 0); -- the duration of the silent period ----

--- ranging delay is the duration of silent period. modify code appropriately ------

--- GLTP2 sif -------------------------------------------

GXTP_ranging_request :in std_logic;

GXTP_ranging_ID :in std_logic_vector(11 downto 0);

GXTP_ranging_PLSu_PLOAM :in std_logic_vector(1 downto 0);

GXTP_ranging_request_service :out std_logic;

---------- i/f to ASP -----------------------------------

Access_str_number_valid :in std_logic;

Access_str_number :in std_logic_vector(13 downto 0);

dark_period_indication :in std_logic;

spec_broad_req_included :in std_logic;

allow_SBA :out std_logic;

Spec_broad_req_as :out std_logic_vector(14 downto 0);

spec_broad_request :out std_logic;
----------- from mem initialiser ---------------------------

FEC_v :in std_logic_vector(127 downto 0); --- vector indicating FEC_enabled ONUs


-- Signals to BW map fifo ------------------

BWmap_fifo_rd : out std_logic;

BWmap_fifo_data : in std_logic_vector(71 downto 0);

BWmap_fifo_empty : in std_logic;

-- GLTP2 i/f -----------------------------

BWmap_valid :out std_logic;

BWmap_onuid :out std_logic_vector(1 downto 0);

BWmap_data :out std_logic_vector(15 downto 0)

);


end component;
----------------------------------------------------------------------

--------------- CRC_insertion ---------------------------------------

----------------------------------------------------------------------

component CRC_insertion is

port(

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

--BWmap fifo i/f

BWmap_fifo_wr :out std_logic;

BWmap_fifo_data :out std_logic_vector(71 downto 0);

--access structure

access_structure_valid : in std_logic;

access_structure : in std_logic_vector(71 downto 8) --this is a 56-bit reg; crc=8 bits are to added afterwards

);


end component; -- entity CRC_insertion;
----------------------------------------------------------------------

component OBUF

port (I : in std_logic;

O : out std_logic);

end component;

----------------------------------------------------------------------


end package GMAC_OLT_pkg;
package body GMAC_OLT_pkg is
--====================================================================

-- Id: A.1

--

-- This procedure simulates the spi interface between GMAC_OLT



-- and OBC

---------------------------------------------------------------------

--translate_off

procedure spi_if(signal spi_in : OUT std_logic;

command : std_logic_vector(7 downto 0);

address : std_logic_vector(7 downto 0);

data : std_logic_vector(7 downto 0)) is

begin


command_label : for i in 7 downto 0 loop

spi_in <= command(i);

wait for 2*spi_clk_half_period;

end loop command_label;

address_label : for i in 7 downto 0 loop

spi_in <= address(i);

wait for 2*spi_clk_half_period;

end loop address_label;

word_label : for i in 7 downto 0 loop

spi_in <= data(i);

wait for 2*spi_clk_half_period;

end loop word_label;


end procedure spi_if;

--translate_on

--====================================================================

-- Id: A.2

--

-- This procedure simulates the spi interface between GMAC_OLT



-- and OBC

---------------------------------------------------------------------

--translate_off

procedure spi_if(signal spi_in : OUT std_logic;

command : integer;

address : integer;

data : integer) is

variable command_v, address_v, data_v : std_logic_vector(7 downto 0);

begin

command_v := conv_std_logic_vector(command,8);



address_v := conv_std_logic_vector(address,8);

data_v := conv_std_logic_vector(data,8);

command_label : for i in 7 downto 0 loop

spi_in <= command_v(i);

wait for 2*spi_clk_half_period;

end loop command_label;

address_label : for i in 7 downto 0 loop

spi_in <= address_v(i);

wait for 2*spi_clk_half_period;

end loop address_label;

word_label : for i in 7 downto 0 loop

spi_in <= data_v(i);

wait for 2*spi_clk_half_period;

end loop word_label;


end procedure spi_if;

--translate_on

--translate_off

--====================================================================

-- Id: A.3

--


-- This procedure simulates the spi interface between GMAC_OLT

-- and OBC

---------------------------------------------------------------------

procedure spi_if(signal spi_in : OUT std_logic;

command : integer;

address : integer;

data : std_logic_vector(7 downto 0)) is

variable command_v, address_v : std_logic_vector(7 downto 0);

begin

command_v := conv_std_logic_vector(command,8);



address_v := conv_std_logic_vector(address,8);

command_label : for i in 7 downto 0 loop

spi_in <= command_v(i);

wait for 2*spi_clk_half_period;

end loop command_label;

address_label : for i in 7 downto 0 loop

spi_in <= address_v(i);

wait for 2*spi_clk_half_period;

end loop address_label;

word_label : for i in 7 downto 0 loop

spi_in <= data(i);

wait for 2*spi_clk_half_period;

end loop word_label;
end procedure spi_if;

--translate_on

--translate_off

--====================================================================

-- Id: A.4

-- This procedure simulates the GLTP interface between GMAC_OLT --

-- and GLTP --

---------------------------------------------------------------------

procedure gxtp_sif_if(signal gxtp_sif_data : OUT std_logic; data

: std_logic_vector(15 downto 0)) is

begin

GXTP_sif_data <= '1'; --SERIAL INTERFACE ACTIVATION...



wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(15); -- Ranging

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(14); -- FFS

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(13); -- PLOAMrequest=1

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(12); -- PLSU=1

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(11); -- 5-16 AllocID....

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(10);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <=data(9);

wait for 2*GXTP_sif_clk_period; ------

GXTP_sif_data <=data(8);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <=data(7);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(6);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <=data(5);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(4);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(3);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(2);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(1);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= data(0);

wait for 2*GXTP_sif_clk_period;

GXTP_sif_data <= '0';

wait for 2*GXTP_sif_clk_period;

end procedure gxtp_sif_if;

--translate_on

--translate_off

Procedure new_allocID_arrival (signal cs : OUT std_logic;

signal mac_mosi : OUT std_logic;

ts1 :integer ; --Transmition Sequence

allocID_data : integer;

ts2 :integer ;

MaxTB_data : integer;

ts3 :integer ;

MinTB_data : integer;

ts4 :integer ;

MaxSDI_data : integer;

ts5 :integer ;

MinSDI_data : integer;

ts6 :integer ;

ResONU_data : std_logic_vector(15 downto 0);

ts7 :integer ;

Frame_Duration_data : integer) IS


variable i : integer;

variable allocID_data_v : std_logic_vector(11 downto 0);

variable maxTB_data_v, minTB_data_v : std_logic_vector(15 downto 0);

variable maxSDI_data_v, minSDI_data_v : std_logic_vector(15 downto 0);

BEGIN

i := 1;


allocID_data_v := conv_std_logic_vector(allocID_data,12);

maxTB_data_v := conv_std_logic_vector(maxTB_data,16);

minTB_data_v := conv_std_logic_vector(minTB_data,16);

maxSDI_data_v := conv_std_logic_vector(maxSDI_data,16);

minSDI_data_v := conv_std_logic_vector(minSDI_data,16);

set_data : loop

if ts1 = i then

-- allocID "00000001" & "00000010"

-------------------------------------------------------------------

cs <= '1';

spi_if(mac_mosi,3,1,conv_integer(allocID_data_v(11 downto 4)));

cs <= '0';

wait for 2*spi_clk_half_period;
cs <= '1';

spi_if(mac_mosi,3,2,conv_integer(allocID_data_v(3 downto 0) & "0000"));

cs <= '0';

wait for 2*spi_clk_half_period; --- added 040210

-------------------------------------------------------------------

elsif ts2 = i then

-- MaxTB "00000011" & "00000100"

-------------------------------------------------------------------

cs <= '1';

spi_if(mac_mosi,3,3,conv_integer(MaxTB_data_v(15 downto 8)));

cs <= '0';

wait for 2*spi_clk_half_period;


cs <= '1';

spi_if(mac_mosi,3,4,conv_integer(MaxTB_data_v(7 downto 0)));

cs <= '0';

wait for 2*spi_clk_half_period; --- added 040210

-------------------------------------------------------------------

elsif ts3 = i then

-- MinTB "00000101" & "00000110"

-------------------------------------------------------------------

cs <= '1';

spi_if(mac_mosi,3,5,conv_integer(MinTB_data_v(15 downto 8)));

cs <= '0';

wait for 2*spi_clk_half_period;


cs <= '1';

spi_if(mac_mosi,3,6,conv_integer(MinTB_data_v(7 downto 0)));

cs <= '0';

wait for 2*spi_clk_half_period; --- added 040210

-------------------------------------------------------------------

elsif ts4 = i then

-- MaxSDI "00000111" & "00001000"

-------------------------------------------------------------------

cs <= '1';

spi_if(mac_mosi,3,7,conv_integer(MaxSDI_data_v(15 downto 8)));

cs <= '0';

wait for 2*spi_clk_half_period;


cs <= '1';

spi_if(mac_mosi,3,8,conv_integer(MaxSDI_data_v(7 downto 0)));

cs <= '0';

wait for 2*spi_clk_half_period; --- added 040210

-------------------------------------------------------------------

elsif ts5 = i then

-- MinSDI "00001001" & "00001010"

-------------------------------------------------------------------

cs <= '1';

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