Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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Дата канвертавання24.04.2016
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c_has_ce => 0,

c_has_aclr => 0,

c_sync_enable => 0,

c_has_ainit => 0,

c_sinit_val => "0",

c_has_sset => 0,

c_has_sinit => 0,

c_has_q => 0,

c_has_o => 1,

c_inputs => 128);

BEGIN
U0 : wrapped_plsu_mux_nr

port map (

M => M,

S => S,


O => O);

END plsu_mux_nr_a;


-- synopsys translate_on

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 11/6/03

-------------------------------------------

-- Design Unit Name :package GMAC_OLT_pkg

-- Purpose : This entity is the package. All the components used at the top

-- level are included as well as the procedure spi_if and

-- gxtp_sif_if.

-- File Name : GMAC_olt_pkg_040206.vhd

-----------------------------------------------------------------------

-----------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use ieee.std_logic_arith.all;


use work.cons_pkg.ALL;

package GMAC_OLT_pkg is


constant spi_clk_half_period : time := 80 ns;

constant gxtp_sif_clk_period : time :=6 ns;

-- ********************* P R O C E D U R E S *********************

===========================================================================

-- Id: A.1

--


-- This procedure simulates the spi interface between GMAC_OLT

-- and OBC

---------------------------------------------------------------------

--translate_off

procedure spi_if(signal spi_in : OUT std_logic;

command : std_logic_vector(7 downto 0);

address : std_logic_vector(7 downto 0);

data : std_logic_vector(7 downto 0));

--============================================================================

-- Id: A.2

--

-- This procedure simulates the spi interface between GMAC_OLT



-- and OBC

---------------------------------------------------------------------

procedure spi_if(signal spi_in : OUT std_logic;

command : integer;

address : integer;

data : integer);

--============================================================================

-- Id: A.3

--

-- This procedure simulates the spi interface between GMAC_OLT



-- and OBC

---------------------------------------------------------------------

procedure spi_if(signal spi_in : OUT std_logic;

command : integer;

address : integer;

data : std_logic_vector(7 downto 0));

---------------------------------------------------------------------

-- This procedure simulates the GLTP_sif interface between GMAC_OLT--

-- and GLTP --

---------------------------------------------------------------------

procedure gxtp_sif_if(signal gxtp_sif_data : OUT std_logic;

data : std_logic_vector(15 downto 0));

-------------------------------------------------------------------

Procedure new_allocID_arrival ( signal cs : OUT std_logic;

signal mac_mosi : OUT std_logic;

ts1 :integer ; --Transmition Sequence

allocID_data : integer;

ts2 :integer ;

MaxTB_data : integer;

ts3 :integer ;

MinTB_data : integer;

ts4 :integer ;

MaxSDI_data : integer;

ts5 :integer ;

MinSDI_data : integer;

ts6 :integer ;

ResONU_data : std_logic_vector(15 downto 0);

ts7 :integer ;

Frame_Duration_data : integer);
--translate_on
----------------------------------------------------------------------

--------- components declaration -------------------------------------

----------------------------------------------------------------------
----------------------------------------------------------------------

--------- SPI2PARALLEL -----------------------------------------------

----------------------------------------------------------------------

component spi2parallel is

port

(

clk : in std_logic; --FPGA's clock



rstn : in std_logic; --Active Low Reset

--SPI i/f

spi_clk : in std_logic; --spi_clk

MAC_mosi : in std_logic; --spi_mosi

MAC_miso : out std_logic; --spi_miso

MAC_cs : in std_logic; --spi_sel

--parallel bus i/f

par_cs : out std_logic;

par_we : out std_logic;

par_addr : out std_logic_vector (7 downto 0); --Parallel address

par_data : out std_logic_vector (7 downto 0); --Parallel data

par2spi_addr : in std_logic_vector (7 downto 0); --Parallel address

par2spi_data : in std_logic_vector (7 downto 0) -- Parallel data

);

end component;


----------------------------------------------------------------------

------------ PARALLEL_BUS --------------------------------------------

----------------------------------------------------------------------

component parallel_bus is

generic (

allocID_gen : positive := 10;

TB_gen : positive := 16;

SDI_gen : positive := 13

);
port

(

clk :in std_logic; --system clock



rstn :in std_logic; --reset negative

--SPI2Par interface

cs : in std_logic; --chip select

we : in std_logic; --Write Enable

addr : in std_logic_vector(7 downto 0); --epilogh tou register pou 8elw na diabasw

din : in std_logic_vector(7 downto 0);

addr2spipar : out std_logic_vector(7 downto 0);

dout : out std_logic_vector(7 downto 0);

--mem_initializer i/f

allocID_valid :out std_logic; --Shkwnetai otan diabasw tous registers efoson ACT/DEACT = 1

allocID :out std_logic_vector(10 downto 0); --0001

MaxTB :out std_logic_vector(15 downto 0); --0010

MinTB :out std_logic_vector(15 downto 0); --0011

MaxSDI :out std_logic_vector(12 downto 0); --0100

MinSDI :out std_logic_vector(12 downto 0); --0101

ResONU :out std_logic_vector(15 downto 0); --ResONU(8)+NSR + TCONT(3)+FEC_enable(1)+piggybacked (1)+Report_mode(2) --0110

ONU_info :out std_logic_vector (9 downto 0); --act/deact + onuID --0111

ONU_valid :out std_logic;

--onu_service i/f

PLOAMint :out std_logic_vector (12 downto 0); --enable + interval --1000


--bwmap_forwarder i/f

Ranging_delay :out std_logic_vector (15 downto 0); --1001

MAC_control :out std_logic_vector (4 downto 0) --1010

);

end component;


----------------------------------------------------------------------

------------ MEM_INITIALIZER -----------------------------------------

----------------------------------------------------------------------

component mem_initializer is

generic (

allocID_gen : positive;

TB_gen : positive;

SDI_gen : positive;

sdi_mem_gen : positive

);
port(

clk : in std_logic;

rstn : in std_logic;


---- Parallel bus i/f ----

AllocID_valid : in std_logic;

AllocId : in std_logic_vector (allocID_gen downto 0);

maxTB : in std_logic_vector (TB_gen - 1 downto 0);

minTB : in std_logic_vector (TB_gen - 1 downto 0);

maxSDI : in std_logic_vector (SDI_gen - 1 downto 0);

minSDI : in std_logic_vector (SDI_gen - 1 downto 0);

resONU : in std_logic_vector (15 downto 0); --ResONU(7)+TCONT(2)+FEC_enable(1)+DBA_reporting(1)+Act/De(1)

--to act/deact einai to ResONU(1)

frame_duration : in std_logic_vector (13 downto 0); --see "parallel_bus" entity for more info upon this

ONU_info : in std_logic_vector (9 downto 0); -- FEC+ act/deact + onuID --0111

ONU_valid : in std_logic;


--ONU service i/f

active_ONUs_ID : out std_logic_vector(127 downto 0);

FEC_enabled_ONUs: out std_logic_vector(127 downto 0);

--mem b port b i/f

sbw_memb_addrb : out std_logic_vector(allocID_gen - 1 downto 0);

sbw_memb_dinb : out std_logic_vector(sdi_mem_gen - 1 downto 0);

sbw_memb_enb : out std_logic;

sbw_memb_web : out std_logic;

----- sbw ti i/f

sbwti_addr : in std_logic_vector(allocID_gen - 1 downto 0);

--bap memory i/f

bap_en : out std_logic;

bap_we : out std_logic;

bap_addr : out std_logic_vector(allocID_gen - 1 downto 0);

bap_douta : out std_logic_vector(47 downto 0);

--to all other components

frame_number :out std_logic_vector(15 downto 0);

fclk : out std_logic

);

end component;


----------------------------------------------------------------------

------------ MAXSDI_MEM -------------------------------------------

----------------------------------------------------------------------

component sdi_mem IS

port (

addra : IN std_logic_VECTOR(9 downto 0);



addrb : IN std_logic_VECTOR(9 downto 0);

clka : IN std_logic;

clkb : IN std_logic;

dina : IN std_logic_VECTOR(14 downto 0);

dinb : IN std_logic_VECTOR(14 downto 0);

douta : OUT std_logic_VECTOR(14 downto 0);

doutb : OUT std_logic_VECTOR(14 downto 0);

ena : IN std_logic;

enb : IN std_logic;

wea : IN std_logic;

web : IN std_logic

);

END component;



component max_sdi_mem IS

port (


addr: IN std_logic_VECTOR(9 downto 0);

clk: IN std_logic;

din: IN std_logic_VECTOR(14 downto 0);

dout: OUT std_logic_VECTOR(14 downto 0);

en: IN std_logic;

we: IN std_logic);

END component;
----------------------------------------------------------------------

------------ GBW_TI --------------------------------------------------

----------------------------------------------------------------------

component gbw_ti is

generic(

allocid_gen : positive := 10;

SDI_gen : positive := 13;

sdi_mem_gen : positive := 15

);
port(

rstn : in std_logic;

clk : in std_logic;

fclk : in std_logic;

--- parallel bus ---------------------------------------------

AllocID_valid : in std_logic;

AllocId : in std_logic_vector (allocID_gen downto 0);

maxSDI : in std_logic_vector (SDI_gen - 1 downto 0);

--------------------------------------------------------------

--maxsdi i/f a

mema_addr : out std_logic_vector(allocid_gen - 1 downto 0);

mema_en : out std_logic;

mema_we : out std_logic;

mema_din : in std_logic_vector(sdi_mem_gen - 1 downto 0); --input from memory 1

mema_dout : out std_logic_vector(sdi_mem_gen - 1 downto 0); --output to memory 1

--maxsdi i/f b

memb_addr : out std_logic_vector(allocid_gen - 1 downto 0);

memb_en : out std_logic;

memb_we : out std_logic; -- .this entity never writes to memB

memb_din : in std_logic_vector(sdi_mem_gen - 1 downto 0); --bit14 = activate

memb_dout : out std_logic_vector(sdi_mem_gen - 1 downto 0);

--bit13 = valid_timer

--afifo i/f --bit12-0 = maxSDI value

fifo_dout : out std_logic_vector(allocid_gen - 1 downto 0);

fifo_we : out std_logic --;

);

end component;


----------------------------------------------------------------------

------------ timers FIFO (asynchronous) -----------------------------

----------------------------------------------------------------------

component afifo_maxsdi IS

port (

din : IN std_logic_VECTOR(9 downto 0);



wr_en : IN std_logic;

wr_clk : IN std_logic;

rd_en : IN std_logic;

rd_clk : IN std_logic;

ainit : IN std_logic;

dout : OUT std_logic_VECTOR(9 downto 0);

full : OUT std_logic;

empty : OUT std_logic;

rd_ack : OUT std_logic;

wr_ack : OUT std_logic

);

END component;


----------------------------------------------------------------------

------------ GBW_TS --------------------------------------------------

----------------------------------------------------------------------

component gbw_ts is

port(

clk : IN std_logic;



rstn : IN std_logic;

fclk : IN std_logic; --frame clock;every time a new frame enters the entity the fclk changes state or completes one period????????


--gbw_ti i/f

allocID_fetch : out std_logic; --this signal may be redandunt

allocID_valid : in std_logic;

allocID : in std_logic_vector(9 downto 0); --allocid from timer_inspection entity

fifo_empty : in std_logic;

--bap & reqmat access

mem_req : out std_logic; --a request to bap_arbiter & reqmat_arbiter in the same time

mem_addr : out std_logic_vector(9 downto 0);


--bap i/f

bap_we : out std_logic;

bap_valid : in std_logic;

bap_param : in std_logic_vector(47 downto 0);


--reqmat i/f

reqmat_we : out std_logic;

reqmat_valid : in std_logic;

reqmat_param : in std_logic_vector(20 downto 0);


--ONU_service i/f

ONU_service_req : out std_logic; --if '1', a request for PLSu, PLOAM from ONU_service

PLSu_PLOAM_valid : in std_logic;

PLSu_PLOAM_flags : in std_logic_vector(1 downto 0);

------ to update reqmat ----------------------------

allocation_bytes :out std_logic_vector(15 downto 0);

update_reqmat_cmd :out std_logic;

request :out std_logic_vector(20 downto 0);

t_cont :out std_logic_vector(1 downto 0);

--asp i/f

GBWstruct_RDY : out std_logic; --this signal serves as an allocid_valid and as RDY signal

GBWstruct_allocid : out std_logic_vector(9 downto 0);

GBWonu_id : out std_logic_vector(7 downto 0);

GBWalloc_bytes : out std_logic_vector(15 downto 0);

GBWpcbu_fec : out std_logic_vector(5 downto 0);

GBWplsu_PLOAM : out std_logic_vector(1 downto 0);

Available_bytes : in std_logic_vector(14 downto 0);

GBW_assigned : out std_logic --guaranteed bandwidth has been assigned, notify the access structure preparation entity

);

end component;


----------------------------------------------------------------------

-- BAP & REQMAT & FLAGS3 & FLAGS4 ARBITER ----------------------------

----------------------------------------------------------------------

component arbiter is

generic(

addr_gen : positive;

mem_width_gen : positive

);

port(



clk : in std_logic;

rstn : in std_logic;


--A i/f

A_addr : in std_logic_vector(addr_gen - 1 downto 0);

A_we : in std_logic;

A_req : in std_logic;

A_ack : out std_logic;

A_din : in std_logic_vector(mem_width_gen - 1 downto 0);

A_dout : out std_logic_vector(mem_width_gen - 1 downto 0);
--B i/f

B_addr : in std_logic_vector(addr_gen - 1 downto 0);

B_we : in std_logic;

B_req : in std_logic;

B_ack : out std_logic;

B_din : in std_logic_vector(mem_width_gen - 1 downto 0);

B_dout : out std_logic_vector(mem_width_gen - 1 downto 0);
--C i/f

C_addr : in std_logic_vector(addr_gen - 1 downto 0);

C_we : in std_logic;

C_req : in std_logic;

C_ack : out std_logic;

C_din : in std_logic_vector(mem_width_gen - 1 downto 0);

C_dout : out std_logic_vector(mem_width_gen - 1 downto 0);
--D i/f

D_addr : in std_logic_vector(addr_gen - 1 downto 0);

D_we : in std_logic;

D_req : in std_logic;

D_ack : out std_logic;

D_din : in std_logic_vector(mem_width_gen - 1 downto 0);

D_dout : out std_logic_vector(mem_width_gen - 1 downto 0);

--memory i/f

mem_addr : out std_logic_vector(addr_gen - 1 downto 0);

mem_en : out std_logic;

mem_we : out std_logic;

mem_dout : out std_logic_vector(mem_width_gen - 1 downto 0);

mem_din : in std_logic_vector(mem_width_gen - 1 downto 0)

);

end component;


----------------------------------------------------------------------

------------ BAP_MEM ----------------------------------------------

----------------------------------------------------------------------

component bap_mem IS

port (

addr: IN std_logic_VECTOR(9 downto 0);



clk : IN std_logic;

din : IN std_logic_VECTOR(47 downto 0);

dout: OUT std_logic_VECTOR(47 downto 0);

en : IN std_logic;

nd : IN std_logic;

rfd : OUT std_logic;

rdy : OUT std_logic;

we : IN std_logic

);

END component;


----------------------------------------------------------------------

------------ REQMAT_MEM -------------------------------------------

----------------------------------------------------------------------

component reqmat_mem IS

port (

addr: IN std_logic_VECTOR(9 downto 0);



clk : IN std_logic;

din : IN std_logic_VECTOR(20 downto 0);

dout: OUT std_logic_VECTOR(20 downto 0);

en : IN std_logic;

nd : IN std_logic;

rfd : OUT std_logic;

rdy : OUT std_logic;

we : IN std_logic

);

END component;


----------------------------------------------------------------------

------------ ONU_SERVICE ---------------------------------------------

----------------------------------------------------------------------

component onu_service is

port( clk : in std_logic;

rstn : in std_logic;

fclk : in std_logic;

--timer service i/f

plsu_ploam_req : in std_logic; --if '1', a request for PLSu, PLOAM from ONU_service

ONUID : in std_logic_vector(7 downto 0);

plsu_ploam_valid : out std_logic;

plsu_ploam : out std_logic_vector(1 downto 0);

pending_urgent_PLOAM_req : in std_logic; --from asp, indicating that the ONU_service will be serviced

ONU_service_struct_valid : out std_logic;

ONU_service_struct_allocID: out std_logic_vector(9 downto 0);

ONU_service_ONU_id : out std_logic_vector(7 downto 0);

ONU_service_alloc_bytes : out std_logic_vector(15 downto 0); --always (others => '0')

ONU_service_pcbu_fec : out std_logic_vector(2 downto 0); --Q: about FEC

ONU_service_assigned : out std_logic; --ONU_service has finished service allocID, surplus follows

--mem_initializer i/f

active_ONUs : in std_logic_vector(127 downto 0); -- indicates which ONUs are active

FEC_v : in std_logic_vector(127 downto 0);

--OBC parallel

PLOAM_interval :in std_logic_vector(11 downto 0);

Regular_PLOAM_mechanism_enable :in std_logic;
-------- GXTP SIF

GXTP_SIF_onuid :in std_logic_vector(7 downto 0);

Explicit_PLOAM_req :in std_logic; ----- assumed active high until GXTP_SIF_req_serviced is activated

Explicit_PLSu_req :in std_logic;----- assumed active high until GXTP_SIF_req_serviced is activated

GXTP_SIF_req_serviced :out std_logic

);


end component;
----------------------------------------------------------------------

------------ GXTP_SIF ------------------------------------------------

----------------------------------------------------------------------

component GXTP_sif is

port(

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

-------GXTP SIF signals -----------------

GXTP_sif_data : in std_logic;

--------- to whom it may concern --------------

GXTP_ranging_request :out std_logic;

GXTP_ranging_ID :out std_logic_vector(11 downto 0);

GXTP_ranging_PLSu_PLOAM :out std_logic_vector(1 downto 0);

GXTP_ranging_request_service :in std_logic;

-------- ONU_service interface -----------------------------

GXTP_SIF_onuid :out std_logic_vector(7 downto 0);

Explicit_PLOAM_req :out std_logic; ----- assumed active high until GXTP_SIF_req_serviced is activated

Explicit_PLSu_req :out std_logic; ----- assumed active high until GXTP_SIF_req_serviced is activated

GXTP_SIF_req_serviced :in std_logic

);


end component;
----------------------------------------------------------------------

------------ ASP -----------------------------------------------------

----------------------------------------------------------------------

component asp is

port(

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

fclk : in std_logic;

--gbw_ts i/f

GBWstruct_valid : in std_logic;

GBWstruct_allocid : in std_logic_vector(9 downto 0); --the allocID number

GBWonu_id : in std_logic_vector(7 downto 0); --the ONU_ID has to be received, as well

GBWalloc_bytes : in std_logic_vector(15 downto 0); --the number of bytes to be allocated/granted

GBWpcbu_fec : in std_logic_vector(5 downto 0); --whether we have FEC or PCBu ; 2 MSBs=PCBu, LSB=FEC

GBWplsu_ploam : in std_logic_vector(1 downto 0);

GBW_assigned : in std_logic; --garanteed bandwidth has been assigned

GBW_ts_en : out std_logic; ------------------------enables the delivery of allocids from ts to asp -----added by nelly on 19/1103

--sbw_ts i/f

SBWstruct_valid : in std_logic;

SBWstruct_allocid : in std_logic_vector(9 downto 0); --the allocID number

SBWonu_id : in std_logic_vector(7 downto 0); --the ONU_ID has to be received, as well

SBWalloc_bytes : in std_logic_vector(15 downto 0); --the number of bytes to be allocated/granted

SBWpcbu_fec : in std_logic_vector(5 downto 0); --whether we have FEC or PCBu ; 2 MSBs=PCBu, LSB=FEC

SBWplsu_ploam : in std_logic_vector(1 downto 0);

SBW_ts_en : out std_logic; ------------------- active 1 -----enables the delivery of allocids from ts to asp -----added by nelly on 19/1103

--gbw_ts & sbw_ts i/f

available_bytes :out std_logic_vector(14 downto 0);

--- onu_po i/f

ONU_po_struct_valid : in std_logic;

ONU_po_struct_allocID: in std_logic_vector(9 downto 0);

ONU_po_ONU_id : in std_logic_vector(7 downto 0);

ONU_po_alloc_bytes : in std_logic_vector(15 downto 0); --always (others => '0')

ONU_po_pcbu_fec : in std_logic_vector(2 downto 0); --Q: about FEC

ONU_po_plsu_ploam : in std_logic_vector(1 downto 0);

ONU_po_assigned : in std_logic; --ONU_po has finished po allocID, surplus follows

ONU_po_en : out std_logic; --from asp, indicating that the ONU_po will be pod

---------- i/f to BW map -----------------------------------

BWmap_header :out std_logic_vector(15 downto 0);

BWmap_header_valid :out std_logic;

allow_SBA : in std_logic;

Spec_broad_req_allocid : in std_logic_vector(11 downto 00);

Spec_broad_req_FEC : in std_logic;

Spec_broad_req_PLSu : in std_logic;

Spec_broad_req_PLOAM : in std_logic;

Spec_broad_req_valid : in std_logic;

--access structure

BWmap_fifo_selection : out std_logic;

access_structure_valid : out std_logic;

access_structure : out std_logic_vector(71 downto 8) --this is a 56-bit reg; crc=8 bits are to added afterwards

);


end component;
----------------------------------------------------------------------

------------ UPDATE_REQMAT -------------------------------------------

----------------------------------------------------------------------

component update_reqmat is

port (

clk :in std_logic;

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