Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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next_normal_dba_state<= receive_header;

when receive_header =>

next_normal_dba_state<= wait_fifo_data;

when wait_fifo_data =>

next_normal_dba_state<=deliver_header;

when deliver_header =>

if BWmap_fifo_empty_d='0' then

next_normal_dba_state<=deliver_word1 ;

else

next_normal_dba_state<= close_delivery ;



end if;

when deliver_word1 =>

next_normal_dba_state<=deliver_word2 ;

when deliver_word2 =>

next_normal_dba_state<=deliver_word3 ;

when deliver_word3 =>

next_normal_dba_state<=deliver_word4 ;

when deliver_word4 =>

if BWmap_fifo_empty ='1' and (deliver_last_word='1' or single_word='1') then

next_normal_dba_state<= close_delivery ;

else

next_normal_dba_state<=deliver_word1 ;



end if;

when close_delivery =>

if fclk='1' then

next_normal_dba_state<= idle ;

else

next_normal_dba_state<= close_delivery ;



end if;

end case;


else -- not normal dba

next_normal_dba_state<=idle;

end if;

end process normal_dba_fsm_proc;


------------------------------------------------------------------------------

------------- initialisation FSM : delivering only BW map header ------------

------------------------------------------------------------------------------

init_fsm_proc : process(current_state, current_init_state, fclk ) is --, fclk, BWmap_delivered ,BWmap_fifo_empty,

begin


if current_state=initialization or current_state = prepare_ranging or current_state = silent2 or current_state = silent1 then ---

case current_init_state is

when idle1 =>

if fclk='1' then

next_init_state<= wait1;

else


next_init_state<= idle1;

end if;


when wait1 =>

next_init_state<= wait2;

when wait2 =>

next_init_state<= wait3;

when wait3 =>

next_init_state<= close;

when close=>

next_init_state<= idle1;

end case;

else


next_init_state<=idle1;

end if;


end process init_fsm_proc;

------------------------------------------------------------------------------

------------------------------------------------------------------------------

-------------- asp signals generation ----------------------------------------

header_proc : process(clk, rstn) is

begin


if rstn = '0' then

header<=(others =>'0');

Spec_broad_req_as_int(11 downto 0) <="000011111110";

Spec_broad_req_as_int(14 downto 12) <= "011";

spec_broad_request_int <='0';

GXTP_ranging_request_d <='0';

elsif rising_edge(clk) then

if Access_str_number_valid='1' then

header(13 downto 0)<= Access_str_number ;

header(14) <= spec_broad_req_included; -- dark_period_indication;

end if;
if current_state = prepare_ranging or current_state = silent2 then -- or current_state = silent1 then ---

if current_init_state=close then

header(15) <='1';

else


header(15) <='0';

end if;


else

header(15) <='0';

end if;

if current_state=silent2 and fclk='1' then



spec_broad_request_int<='1';

else


spec_broad_request_int<='0';

end if;


GXTP_ranging_request_d<=GXTP_ranging_request;

if regular_ranging_established='0' then

Spec_broad_req_as_int<=requested_rangingID;

else --if counter="00000000001" and enable_regular_ranging ='1' and current_state=normal_dba then

Spec_broad_req_as_int (11 downto 0) <="000011111110";

Spec_broad_req_as_int(13 downto 12) <= "11";

Spec_broad_req_as_int(14) <='0'; -- FEC flag

end if;


end if;

end process header_proc;


requested_ID_proc: process(clk, rstn) is

begin


if rstn = '0' then

requested_rangingID<=(others =>'0');

regular_ranging_established<='0';

regular_ranging_pending<='0' ;

wait_prepare_ranging<='0';

elsif rising_edge(clk) then

if GXTP_ranging_request='1' and GXTP_ranging_request_d='0' then

requested_rangingID (11 downto 0) <= GXTP_ranging_ID;

requested_rangingID(13 downto 12) <= GXTP_ranging_PLSu_PLOAM;

requested_rangingID(14) <=FEC_v(conv_integer(GXTP_ranging_ID(6 downto 0)));

end if;

if (current_state= INITIALIZATION or current_state= normal_dba) and ((counter = "00000000001" and enable_regular_ranging = '1') or regular_ranging_pending='1') then

regular_ranging_established<='1';

elsif spec_broad_request_int='1' and Spec_broad_req_as_int (14 downto 0) <="011000011111110" then

regular_ranging_established<='0';

end if;


if (counter = "00000000001" and enable_regular_ranging = '1') and (NOT (current_state=normal_DBA or current_state=initialization) )then

regular_ranging_pending<='1' ;

elsif wait_prepare_ranging='1' and current_state=prepare_ranging then

regular_ranging_pending<='0' ;

end if;

if regular_ranging_pending='1' and current_state=normal_dba then



wait_prepare_ranging<='1';

else


wait_prepare_ranging<='0';

end if;


end if;

end process requested_ID_proc;

end architecture BWmap_forwarder_b;

---------------------------------------------------------------------------

-- Project: GIANT

-- MAC controller

-- Date : 06-12-2003

-- Designer : Nelly Leligou

-- Entity : ONU service

-- Version :2a


-- Description

-- This entity maintains the PLSu request vector and the PLOAM request vector.

-- Each ONU corresponds to one bit in these two vectors. Hence, when an access

-- structure is formed this entity provides the PLOAM, PLSu flags. These are

-- ONU oriented operations justifying the name of the entity.The request

-- vectors are set when an explicit request arrives through the GLTP2 SIF.

-- Additionally, when the "regular PLOAM granting mechanism" is enabled, all

-- ONUs receive a PLOAM grant at least every PLOAM interval.When the PLOAM

-- timer expires, all pending requests are serviced, i.e. an access structure

-- granting only PLSu and/or PLOAM overheads is programmed.

--

-- NOTES:



-- 1. ALL requests are satisfied when the PLOAM timer expires.

-- Hence, the PLOAMtimer has to be set even if the regular PLOAM mechanism is disabled.

-- 2. ONU ids 0 to 127 are supported.

-- 3. When the PLOAM timer expires, ONU assigned will be activated about 250 clock periods after

-- the respective ASP triggering in the worst case where all 127 onus are active and all of them

-- deserve service from the ONU service.

-- 4. Verified using TB_onu_service_v2a.

--


-- Assumptions:

-- 1. On the SIF interface: Explicit reqs for PLSu and PLOAM signals are

-- assumed active high until GXTP_SIF_req_serviced is activated

-- 2. On the ASP interface: The minimum distance between two onu_struct_valid rising edges is 3 clock periods

-- pending_urgent_PLOAM_req

--

--



-------------------------------------------------------------------------------

-----------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


----------------------------

entity onu_service is

port( clk : in std_logic;

rstn : in std_logic;

fclk :in std_logic;

--timer service i/f

plsu_ploam_req : in std_logic; --if '1', a request for PLSu, PLOAM from ONU_service

ONUID : in std_logic_vector(7 downto 0);


--access structure preparation i/f

plsu_ploam_valid : out std_logic;

plsu_ploam : out std_logic_vector(1 downto 0);

pending_urgent_PLOAM_req : in std_logic; --from asp, indicating that the ONU_service will be serviced

ONU_service_struct_valid : out std_logic;

ONU_service_struct_allocID: out std_logic_vector(9 downto 0);

ONU_service_ONU_id : out std_logic_vector(7 downto 0);

ONU_service_alloc_bytes : out std_logic_vector(15 downto 0);

ONU_service_pcbu_fec : out std_logic_vector(2 downto 0);

ONU_service_assigned : out std_logic;

--mem_initializer i/f

active_ONUs : in std_logic_vector(127 downto 0); -- indicates which ONUs are active

FEC_v : in std_logic_vector(127 downto 0);
--parallel_bus

PLOAM_interval :in std_logic_vector(11 downto 0);

Regular_PLOAM_mechanism_enable :in std_logic;
-------- GXTP SIF

GXTP_SIF_onuid :in std_logic_vector(7 downto 0);

Explicit_PLOAM_req :in std_logic; ----- assumed active high until GXTP_SIF_req_serviced is activated

Explicit_PLSu_req :in std_logic; ----- assumed active high until GXTP_SIF_req_serviced is activated

GXTP_SIF_req_serviced :out std_logic

);


end entity onu_service;

--------------------------------

architecture onu_service_a of onu_service is
constant PLSU_length :integer range 0 to 255 :=120;

constant PLOAM_length :integer range 0 to 32 :=13;


type TStates is ( idle , service_urgent_req, wait_state1, wait_state2, wait_state3, wait_state4,

wait_state5, wait_state6, wait_state7, last_wait_state);

signal current_state, next_state : TStates;

signal PLSu_reqs_reg : std_logic_vector(127 downto 0); -- keeps the explicit PLSu request announced by ONUs

signal PLOAM_reqs_reg : std_logic_vector(127 downto 0); -- Is set equal to Active ONUs in regular time intervals, from OBC

signal urgent_PLSu : std_logic_vector(127 downto 0);

signal urgent_PLOAM : std_logic_vector(127 downto 0);

signal regular_PLOAM_service : std_logic; -- indicates the frame that the pending requests have to be serviced even not piggybacked

signal address : integer range 0 to 127;

signal ONUID_int : std_logic_vector(6 downto 0);

signal GXTP_SIF_onuid_int : std_logic_vector(6 downto 0);

signal urgent_requests_serviced : std_logic;

signal AllocID : std_logic_vector(9 downto 0);

signal allocid_valid_int : std_logic;

signal plsu_ploam_req_int : std_logic;

signal not_inspected : std_logic;

signal PLOAM_timer : std_logic_vector(11 downto 0);

signal urgent_PLSu_s : std_logic;

signal urgent_PLOAM_s : std_logic;

signal FEC_onu : std_logic;

signal PLSu_ploam_s : std_logic_vector(1 downto 0);

component plsu_mux_nr

port (

M: IN std_logic_VECTOR(127 downto 0);



S: IN std_logic_VECTOR(6 downto 0);

O: OUT std_logic);

END component;

begin
GXTP_SIF_onuid_int <=GXTP_SIF_onuid(6 downto 0);

ONUID_int <=ONUID(6 downto 0);

ONU_service_assigned <=urgent_requests_serviced;

ONU_service_pcbu_fec(2 downto 1) <= "00";
plsu_mux: plsu_mux_nr

port map (

M=> PLSu_reqs_reg, --: IN std_logic_VECTOR(127 downto 0);

S=> ONUID_int, --: IN std_logic_VECTOR(6 downto 0);

O=> PLSu_ploam_s(1)

) ; --: OUT std_logic);


ploam_mux: plsu_mux_nr

port map (

M=> PLOAM_reqs_reg, --: IN std_logic_VECTOR(127 downto 0);

S=> ONUID_int, --: IN std_logic_VECTOR(6 downto 0);

O=> PLSu_ploam_s(0)

); --: OUT std_logic);


process(clk, rstn) is

begin


if rstn = '0' then

current_state <= idle;

elsif rising_edge(clk) then

current_state <= next_state;

end if;

end process;



--

----------------- F S M ---------------

-- When "pending_urgent_PLOAM_req" is set we enter the "service_urgent_req" state until we

-- finish the service all the PLOAM requests

-------------------------

fsm_proc:process(next_state, current_state, pending_urgent_PLOAM_req, address, regular_PLOAM_service,

urgent_PLSU, urgent_PLOAM, not_inspected ) is

begin


case current_state is

when idle =>

if pending_urgent_PLOAM_req='1' and regular_PLOAM_service='1' then

next_state<=service_urgent_req;

else

next_state<=idle;



end if;

when service_urgent_req =>

if address=127 then

next_state<=wait_state1;

else

if (urgent_PLSU(address)='1' or urgent_PLOAM(address) = '1') then



next_state<=wait_state1;

else


next_state<= service_urgent_req;

end if;


end if;

when wait_state1 =>

next_state<=wait_state2;

when wait_state2 =>

next_state<=wait_state3;

when wait_state3 =>

next_state<=wait_state4;

when wait_state4 =>

next_state<=wait_state5;

when wait_state5 =>

next_state<=wait_state6;

when wait_state6 =>

next_state<=wait_state7;

when wait_state7 =>

next_state<= last_wait_state;

when last_wait_state =>

if address=127 then

if not_inspected='1' then

next_state<=idle;

else


next_state<= service_urgent_req;

end if;


else

next_state<= service_urgent_req;

end if;

end case;

end process ;

FEC_onu <=FEC_v(address);

-------------------------------------------------------------------------

---- preparation of the output towards ASP --------------------

process(clk, rstn) is

begin


if rstn = '0' then

plsu_ploam_valid <= '0';

plsu_ploam <= "00";
PLSu_reqs_reg <= (others =>'0');

GXTP_SIF_req_serviced <= '0';

PLOAM_reqs_reg <=(others =>'0');

urgent_PLSu_s <= '0';

urgent_PLOAM_s <= '0';

ONU_service_pcbu_fec(0) <= '0';

plsu_ploam_req_int <='0';

elsif rising_edge(clk) then


plsu_ploam_req_int <=plsu_ploam_req;
--------- plsu and ploam signal to asp ----------------------

if plsu_ploam_req = '1' then --if an ONU has requested grants, then

plsu_ploam_valid <= '1'; --send a valid signal indicating that valid information follows, saying that

--the specific onu has or has not plsu overhead

else

plsu_ploam_valid<='0';



end if;

--------------------------------------------------------------

if current_state=service_urgent_req then

urgent_PLSu_s <=urgent_PLSu(address);

urgent_PLOAM_s <=urgent_PLOAM(address);

ONU_service_pcbu_fec(0) <=FEC_v(address);

end if;

if current_state= idle then

plsu_ploam(1) <= PLSu_ploam_s(1); --PLSu_reqs_reg(conv_integer(ONUID_int));

plsu_ploam(0) <= PLSu_ploam_s(0); --PLOAM_reqs_reg(conv_integer(ONUID_int));

else --if plsu_ploam_req_int = '1' then

plsu_ploam(1) <=urgent_PLSU_s;

plsu_ploam(0) <=urgent_PLOAM_s;

end if;


----------- Assertion of explicit PLSu req bits -----------------

if plsu_ploam_req_int = '1' then

PLSu_reqs_reg(conv_integer(ONUID_int))<='0';

elsif current_state= service_urgent_req then

PLSu_reqs_reg <=(others =>'0');

elsif current_state=idle and Explicit_PLSu_req='1' then

PLSu_reqs_reg(conv_integer(GXTP_SIF_onuid_int))<='1';

end if;
----------------------------------------------

if (Explicit_PLOAM_req='1' or Explicit_PLSu_req='1') and plsu_ploam_req_int='0' and current_state=idle then

GXTP_SIF_req_serviced<='1';

else

GXTP_SIF_req_serviced<='0';



end if;

---------------------------------------------------------------------------

------------- regular_ploam requests ---------------------------------------

if plsu_ploam_req_int = '1' then

PLOAM_reqs_reg(conv_integer(ONUID_int)) <='0';

elsif current_state= service_urgent_req and regular_PLOAM_service = '1' then

if Regular_PLOAM_mechanism_enable='1' then

PLOAM_reqs_reg<=active_ONUs;

else

PLOAM_reqs_reg<=(others =>'0');



end if;

elsif current_state = idle and Explicit_PLOAM_req = '1' then

PLOAM_reqs_reg(conv_integer(GXTP_SIF_onuid_int)) <= '1';

end if;


----------------------------------------------------------------------------

end if;


end process;
ONU_service_alloc_bytes(15 downto 8)<="00000000";

allocID(9 downto 7)<="000";

process(clk, rstn) is

begin


if rstn = '0' then

urgent_PLSU<=(others =>'0');

urgent_PLOAM<=(others =>'0');

address<=0;

AllocID_valid_int<='0';

allocID(6 downto 0)<=(others =>'0');

urgent_requests_serviced<='0';

ONU_service_struct_valid <='0';

ONU_service_struct_allocID <=(others =>'0');

ONU_service_ONU_id <= (others =>'0'); --allocID(6 downto 0);

ONU_service_alloc_bytes(7 downto 0) <= (others =>'0');

regular_PLOAM_service <='0';

not_inspected <='0';

PLOAM_timer <="000000000001";

elsif rising_edge(clk) then
if pending_urgent_PLOAM_req='1' and regular_ploam_service='1'then

urgent_PLSU <= PLSu_reqs_reg;

urgent_PLOAM <= PLOAM_reqs_reg;

end if;


if PLOAM_timer=1 and fclk='1' then

regular_PLOAM_service <= '1';

elsif current_state= service_urgent_req then ---------------

regular_PLOAM_service<='0';

end if;
if fclk='1' then

if PLOAM_timer=1 then

PLOAM_timer<=PLOAM_interval;

else


PLOAM_timer<=PLOAM_timer-1;

end if;


end if;

----------------------------------------------------------------------------

if (address=127 or (pending_urgent_PLOAM_req='1' and regular_PLOAM_service='0')) and current_state=idle then --and urgent_PLSu_word=X"0000" and urgent_PLOAM=X"0000" then

urgent_requests_serviced<='1';

else

urgent_requests_serviced<='0';



end if;

if current_state= service_urgent_req then

if address<127 then

address<=address+1;

end if;

elsif current_state=idle then



address<=0;

end if;


if current_state= wait_state6 and address=127 and (not_inspected ='0') then

not_inspected<='1';

elsif current_state=idle then

not_inspected<='0';

end if;

if current_state=service_urgent_req and ((urgent_PLSU(address)='1' or urgent_PLOAM(address) = '1')) then



AllocID_valid_int<='1';

allocID(6 downto 0)<= conv_std_logic_vector(address, 7);

else

AllocID_valid_int<='0';



end if;
----------- Allocation bytes definition -----------------------------------

if current_state=service_urgent_req then

if FEC_onu='0' then

if urgent_PLSU(address)='1' and urgent_PLOAM(address) = '1' then

ONU_service_alloc_bytes(7 downto 0) <=conv_std_logic_vector((PLSU_length+PLOAM_length), 8);

elsif urgent_PLSU(address)='1' and urgent_PLOAM(address) = '0' then

ONU_service_alloc_bytes(7 downto 0) <=conv_std_logic_vector(PLSU_length, 8);

elsif urgent_PLSU(address)='0' and urgent_PLOAM(address) = '1' then

ONU_service_alloc_bytes (7 downto 0) <=conv_std_logic_vector(PLOAM_length, 8);

end if;


else

if urgent_PLSU(address)='1' and urgent_PLOAM(address) = '1' then

ONU_service_alloc_bytes(7 downto 0) <=conv_std_logic_vector((PLSU_length+PLOAM_length+16), 8);

elsif urgent_PLSU(address)='1' and urgent_PLOAM(address) = '0' then

ONU_service_alloc_bytes(7 downto 0) <=conv_std_logic_vector(PLSU_length+16, 8);

elsif urgent_PLSU(address)='0' and urgent_PLOAM(address) = '1' then

ONU_service_alloc_bytes(7 downto 0) <=conv_std_logic_vector(PLOAM_length+16, 8);

end if;


end if;

end if;


-------------------------------------------------------------------------------------------

ONU_service_struct_valid <=AllocID_valid_int;

ONU_service_struct_allocID <=allocID(9 downto 0);

ONU_service_ONU_id <=allocID(7 downto 0);

----------------------------------------------------------------------------
end if;
end process;
----------------------------------------------

end architecture onu_service_a;


-------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used -

-- solely for design, simulation, implementation and creation of -

-- design files limited to Xilinx devices or technologies. Use -

-- with non-Xilinx devices or technologies is expressly prohibited -

-- and immediately terminates your license. -

-- -


-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -

-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -

-- FOR A PARTICULAR PURPOSE. -

-- -


-- Xilinx products are not intended for use in life support -

-- appliances, devices, or systems. Use in such applications are -

-- expressly prohibited. -

-- -


-- (c) Copyright 1995-2003 Xilinx, Inc. -

-- All rights reserved. -

-------------------------------------------------------------------------------

-- You must compile the wrapper file plsu_mux_nr.vhd when simulating

-- the core, plsu_mux_nr. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Guide".
-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY plsu_mux_nr IS

port (

M: IN std_logic_VECTOR(127 downto 0);



S: IN std_logic_VECTOR(6 downto 0);

O: OUT std_logic);

END plsu_mux_nr;
ARCHITECTURE plsu_mux_nr_a OF plsu_mux_nr IS
component wrapped_plsu_mux_nr

port (


M: IN std_logic_VECTOR(127 downto 0);

S: IN std_logic_VECTOR(6 downto 0);

O: OUT std_logic);

end component;


-- Configuration specification

for all : wrapped_plsu_mux_nr use entity XilinxCoreLib.C_MUX_BIT_V6_0(behavioral)


generic map(

c_has_aset => 0,

c_sync_priority => 1,

c_has_sclr => 0,

c_height => 0,

c_enable_rlocs => 1,

c_sel_width => 7,

c_latency => 0,

c_ainit_val => "0",

c_pipe_stages => 0,

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