Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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---------- signals to CRC module --------------

if current_state=write_fifo then

CRC_rst<='0';

else

CRC_rst <='1';



end if;
if current_state = receive_crc or current_state= idle or current_state= write_fifo then

CRC_input_valid<='0';

else

CRC_input_valid<='1';



end if;

--- forward to CRC module the data -------------------------------

case current_state is

when add_word1=>

CRC_input_data<=access_structure(63 downto 56);

when add_word2=>

CRC_input_data<=access_structure_int_reg(55 downto 48);

when add_word3=>

CRC_input_data<=access_structure_int_reg(47 downto 40);

when add_word4=>

CRC_input_data<=access_structure_int_reg(39 downto 32);

when add_word5=>

CRC_input_data<=access_structure_int_reg(31 downto 24);

when add_word6=>

CRC_input_data<=access_structure_int_reg(23 downto 16);

when add_word7=>

CRC_input_data<=access_structure_int_reg(15 downto 8);

when others =>

CRC_input_data<=(others =>'0');

end case;

---------------------------------------

if access_structure_valid ='1' then

access_structure_int_reg <=access_structure(55 downto 8);

end if;


if current_state=add_word1 then

BWmap_fifo_data(71 downto 8) <=access_structure;

end if;

if CRC_output_valid='1' then



BWmap_fifo_data(7 downto 0) <=CRC_output;

end if;


if current_state=write_fifo then

BWmap_fifo_wr<='1';

else

BWmap_fifo_wr<='0';



end if;

end if; -- clk

end process;
---------------------------

end ; --architecture CRC_insertion_a;

LIBRARY ieee;

use ieee.std_logic_1164.all;


entity CRC8 is
port(CRC8_clk : in std_logic;

CRC8_resetn : in std_logic;

CRC8_data_i : in std_logic_vector(7 downto 0);

CRC8_data_vld_i : in std_logic;

CRC8_data_o : out std_logic_vector(7 downto 0);

CRC8_data_vld_o : out std_logic

);
end CRC8;
architecture RTLS of CRC8 is
signal CRC8_REG,CRC8_REG_INP: std_logic_vector(7 downto 0);

signal CRC8VLD_REG, CRC8VLD_REG_INP : std_logic;


begin
CRC8_data_o <= CRC8_REG;

CRC8_data_vld_o <= CRC8VLD_REG;

CRC8_SEQ : process(CRC8_clk, CRC8_resetn)

begin


if (CRC8_resetn = '0') then

CRC8_REG <= (others=>'0');

CRC8VLD_REG <= '0';

elsif (CRC8_clk'event and CRC8_clk='1') then

CRC8_REG <= CRC8_REG_INP;

CRC8VLD_REG <= CRC8VLD_REG_INP;

end if;

end process CRC8_SEQ;



CRC8_CON : process(CRC8_REG, CRC8VLD_REG, CRC8_data_i, CRC8_data_vld_i)

begin


-- Convention adopted: the first serial data bit is CRC8_data_i(7)

CRC8_REG_INP <= CRC8_REG;

CRC8VLD_REG_INP <= CRC8VLD_REG;

if (CRC8_data_vld_i='1') then

CRC8_REG_INP(0) <= CRC8_data_i(7) xor CRC8_data_i(6) xor CRC8_data_i(0) xor CRC8_REG(0) xor CRC8_REG(6) xor CRC8_REG(7);

CRC8_REG_INP(1) <= CRC8_data_i(6) xor CRC8_data_i(1) xor CRC8_data_i(0) xor CRC8_REG(0) xor CRC8_REG(1) xor CRC8_REG(6);

CRC8_REG_INP(2) <= CRC8_data_i(6) xor CRC8_data_i(2) xor CRC8_data_i(1) xor CRC8_data_i(0) xor CRC8_REG(0) xor CRC8_REG(1) xor CRC8_REG(2) xor CRC8_REG(6);

CRC8_REG_INP(3) <= CRC8_data_i(7) xor CRC8_data_i(3) xor CRC8_data_i(2) xor CRC8_data_i(1) xor CRC8_REG(1) xor CRC8_REG(2) xor CRC8_REG(3) xor CRC8_REG(7);

CRC8_REG_INP(4) <= CRC8_data_i(4) xor CRC8_data_i(3) xor CRC8_data_i(2) xor CRC8_REG(2) xor CRC8_REG(3) xor CRC8_REG(4);

CRC8_REG_INP(5) <= CRC8_data_i(5) xor CRC8_data_i(4) xor CRC8_data_i(3) xor CRC8_REG(3) xor CRC8_REG(4) xor CRC8_REG(5);

CRC8_REG_INP(6) <= CRC8_data_i(6) xor CRC8_data_i(5) xor CRC8_data_i(4) xor CRC8_REG(4) xor CRC8_REG(5) xor CRC8_REG(6);

CRC8_REG_INP(7) <= CRC8_data_i(7) xor CRC8_data_i(6) xor CRC8_data_i(5) xor CRC8_REG(5) xor CRC8_REG(6) xor CRC8_REG(7);

CRC8VLD_REG_INP <= '1';

end if;


end process CRC8_CON;
end RTLS;

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 16/11/03

-------------------------------------------

-- Design Unit Name : BWmap_fifo_mux

-- Purpose : It regulates the access of the crc_insertion and

-- the BWmap_forwarder to the BWmap FIFOs.

--

-- File Name : BWmap_fifo_mux.vhd



-------------------------------------------

-- Description ----------------------------

-- During each frame, the CRC_insertion writes a BWmap in one BWmap fifo while

-- the BWmap_forwarder reads the other bwmap_FIFO to send towards the GLTP2.

-- This means that the BWmap forwarded to the GLTP2 in every frame, has been

-- calculated (by the TS, asp and crc_insertion entities) during the previous frame.

-------------------------------------------

-- Design note: The selection between the two FIFOs is driven by the asp.

---------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


entity BWmap_fifo_mux is

port(


--- CRC_insertion ----------------------------------------

BWmap_fifo_wr :in std_logic;

BWmap_data2fifo :in std_logic_vector(71 downto 0);

--- BW map forwarder ----------------------------

BWmap_fifo_rd : in std_logic;

BWmap_fifo_data : out std_logic_vector(71 downto 0);

BWmap_fifo_empty : out std_logic;

BWmap_fifo_selection :in std_logic;

--BWmap fifo 1 i/f

BWmap_fifo1_rd :out std_logic;

BWmap_fifo1_wr :out std_logic;

BWmap_fifo1_empty :in std_logic;

BWmap_data2fifo1 :out std_logic_vector(71 downto 0);

BWmap_data2entity1 :in std_logic_vector(71 downto 0);


--BWmap fifo 1 i/f

BWmap_fifo2_rd :out std_logic;

BWmap_fifo2_wr :out std_logic;

BWmap_fifo2_empty :in std_logic;

BWmap_data2fifo2 :out std_logic_vector(71 downto 0);

BWmap_data2entity2 :in std_logic_vector(71 downto 0)

);

end; -- entity BWmap_fifo_mux;



--------------------------------

architecture BWmap_fifo_mux_b of BWmap_fifo_mux is


------------------------------------------------------------------------------

begin


process(BWmap_fifo_selection,

BWmap_fifo_wr, BWmap_fifo_rd, BWmap_data2entity2, BWmap_fifo2_empty ,

BWmap_data2fifo , BWmap_data2entity1, BWmap_fifo1_empty )

begin


if BWmap_fifo_selection='1' then

BWmap_fifo1_rd <='0'; -- CRC insertion writes fifo 1

BWmap_fifo1_wr <=BWmap_fifo_wr;

BWmap_data2fifo1 <=BWmap_data2fifo ;

BWmap_fifo2_wr <='0';

BWmap_fifo2_rd <=BWmap_fifo_rd ;-- BWmap forwarder ----------

BWmap_fifo_data <=BWmap_data2entity2;

BWmap_fifo_empty <=BWmap_fifo2_empty ;

else

BWmap_fifo2_rd <='0'; -- CRC insertion writes fifo 2 -



BWmap_fifo2_wr <=BWmap_fifo_wr;

BWmap_data2fifo2 <=BWmap_data2fifo ;

BWmap_fifo1_wr <='0';

BWmap_fifo1_rd <=BWmap_fifo_rd ;-- BWmap forwarder reads fifo 1

BWmap_fifo_data <=BWmap_data2entity1;

BWmap_fifo_empty <=BWmap_fifo1_empty ;

end if;

end process;

end ; --architecture BWmap_fifo_mux_a;

------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--


-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"

-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--


-- Xilinx products are not intended for use in life support

-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--


-- (c) Copyright 1995-2003 Xilinx, Inc.

-- All rights reserved.

------------------------------------------------------------------------------

-- You must compile the wrapper file bwmap_fifo.vhd when simulating

-- the core, bwmap_fifo. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).


-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY bwmap_fifo IS

port (

clk: IN std_logic;



sinit: IN std_logic;

din: IN std_logic_VECTOR(71 downto 0);

wr_en: IN std_logic;

rd_en: IN std_logic;

dout: OUT std_logic_VECTOR(71 downto 0);

full: OUT std_logic;

empty: OUT std_logic);

END bwmap_fifo;


ARCHITECTURE bwmap_fifo_a OF bwmap_fifo IS
component wrapped_bwmap_fifo

port (


clk: IN std_logic;

sinit: IN std_logic;

din: IN std_logic_VECTOR(71 downto 0);

wr_en: IN std_logic;

rd_en: IN std_logic;

dout: OUT std_logic_VECTOR(71 downto 0);

full: OUT std_logic;

empty: OUT std_logic);

end component;
-- Configuration specification

for all : wrapped_bwmap_fifo use entity XilinxCoreLib.sync_fifo_v4_0(behavioral)


generic map(

c_read_data_width => 72,

c_has_wr_ack => 0,

c_dcount_width => 1,

c_has_wr_err => 0,

c_wr_err_low => 1,

c_wr_ack_low => 0,

c_enable_rlocs => 0,

c_has_dcount => 0,

c_rd_err_low => 1,

c_rd_ack_low => 0,

c_read_depth => 512,

c_has_rd_ack => 0,

c_write_depth => 512,

c_ports_differ => 0,

c_memory_type => 1,

c_write_data_width => 72,

c_has_rd_err => 0);

BEGIN
U0 : wrapped_bwmap_fifo

port map (

clk => clk,

sinit => sinit,

din => din,

wr_en => wr_en,

rd_en => rd_en,

dout => dout,

full => full,

empty => empty);

END bwmap_fifo_a;
-- synopsys translate_on

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-------------------------------------------

--------------------------------------------------------------------

-- Design Unit Name : BWmap_forwarder

-- Purpose : This entity is responsible for the handling of silent periods

-- and the final delivery of the BW map to the GLTP2

--

-- Description:



-- For the delivery of the BW map including the ONU id, it reads the

-- BWmapFIFO.This operation is controlled by the "normal_dba_state" FSM

-- (clock level FSM).For the establishment of silent periods a frame-level

-- FSM is implemented.

--

-- File Name : BWmap_forwarder_040205.vhd



-- Assumptions:

-- 1. The GXTP_sif_ranging_request should be active for at least one fclk high period.

-- 2. The regular ranging request is on the port and not generated internally.

-- revision 1: (040127) spec_broad_req_as is changed to 14 downto 0 to include the FEC flag as well.

--------------------------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


----------------------------

entity BWmap_forwarder is

port (

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

fclk : in std_logic;

-- parallel_bus i/f ---------------------------------------

enable_regular_ranging :in std_logic;

regular_ranging_interval :in std_logic_vector(11 downto 0);

------------- start and enable regular ranging is substituted by enable_regular_ranging and regular_ranging_interval

------------- the latter is the programmed value and a timer equal to this is maintained. When it expires,

--------------- ranging has to be performed.

ranging_delay :in std_logic_vector(2 downto 0); -- the duration of the silent period, not currently used ----

--- GLTP2 sif -------------------------------------------

GXTP_ranging_request :in std_logic;

GXTP_ranging_ID :in std_logic_vector(11 downto 0);

GXTP_ranging_PLSu_PLOAM :in std_logic_vector(1 downto 0);

GXTP_ranging_request_service :out std_logic;

---------- i/f to ASP -----------------------------------

Access_str_number_valid :in std_logic;

Access_str_number :in std_logic_vector(13 downto 0);

dark_period_indication :in std_logic;

spec_broad_req_included :in std_logic;

allow_SBA :out std_logic;

Spec_broad_req_as :out std_logic_vector(14 downto 0);

spec_broad_request :out std_logic;

----------- from mem initialiser ---------------------------

FEC_v :in std_logic_vector(127 downto 0); --- vector indicating FEC_enabled ONUs

-- Signals to BW map fifo ------------------

BWmap_fifo_rd : out std_logic;

BWmap_fifo_data : in std_logic_vector(71 downto 0);

BWmap_fifo_empty : in std_logic;

-- GLTP2 i/f -----------------------------

BWmap_valid :out std_logic;

BWmap_onuid :out std_logic_vector(1 downto 0);

BWmap_data :out std_logic_vector(15 downto 0)

);

end; -- entity BWmap_forwarder;



--------------------------------

architecture BWmap_forwarder_b of BWmap_forwarder is

type TStates is (INITIALIZATION, PREPARE_RANGING, SILENT1, SILENT2,

AFTER_SILENT, NORMAL_DBA);

signal current_state, next_state : TStates;

type normal_dba_states is (idle, receive_header, wait_fifo_data, deliver_header, deliver_word1, deliver_word2,

deliver_word3, deliver_word4, close_delivery) ;

signal current_normal_dba_state, next_normal_dba_state : normal_dba_states;

type init_states is (idle1, wait1, wait2, wait3, close);

signal current_init_state, next_init_state : init_states;

signal allow_sba_int :std_logic;

signal deliver_last_word :std_logic;

signal single_word :std_logic;

signal BWmap_fifo_data_int :std_logic_vector(71 downto 0);

signal zero_reg :std_logic_vector(15 downto 0);

signal header :std_logic_vector(15 downto 0);

signal BWmap_fifo_empty_d :std_logic;

signal fclk_d :std_logic;

signal counter :std_logic_vector(11 downto 0);

signal GXTP_ranging_request_d :std_logic;

signal BWmap_data_int :std_logic_vector(15 downto 0);

signal BWmap_valid_int :std_logic;

signal BWmap_onuid_int :std_logic_vector(1 downto 0);

signal Spec_broad_req_as_int :std_logic_vector(14 downto 0);

signal requested_rangingID :std_logic_vector(14 downto 0);

signal spec_broad_request_int : std_logic;

signal regular_ranging_established : std_logic;

signal regular_ranging_pending : std_logic;

signal wait_prepare_ranging: std_logic;

---------------------------------------------------------------------------------------

begin
allow_sba<=allow_sba_int;

Spec_broad_req_as<=Spec_broad_req_as_int;

spec_broad_request<=spec_broad_request_int;
-- #########################################################

----------------- FRAME LEVEL FSM -------------------------

-- #########################################################
init_proc : process(clk, rstn) is

begin


if rstn = '0' then

current_state <= INITIALIZATION;

elsif rising_edge(clk) then

if fclk='1' then

current_state <= next_state;

else


current_state <= current_state;

end if;


end if;

end process init_proc;

---------------

fsm_proc : process(current_state, counter, enable_regular_ranging, regular_ranging_pending,

GXTP_ranging_request ) is

begin
case current_state is

when INITIALIZATION =>

if (counter = "00000000001" and enable_regular_ranging = '1') or ( regular_ranging_pending='1' ) OR GXTP_ranging_request = '1' then

next_state <= PREPARE_RANGING;

else


next_state <= INITIALIZATION;

end if;


when PREPARE_RANGING =>

next_state <= SILENT1;

when SILENT1 =>

next_state <= SILENT2;

when SILENT2 =>

next_state <= AFTER_SILENT;

when AFTER_SILENT =>

next_state <= NORMAL_DBA;

when NORMAL_DBA =>

if (counter="00000000001" and enable_regular_ranging = '1') or ( regular_ranging_pending='1' ) or (GXTP_ranging_request = '1') then

next_state <= PREPARE_RANGING;

else


next_state <= NORMAL_DBA;

end if;
end case;

end process fsm_proc;
-- #########################################################

--$$$$$$$$$$$$ ENTITY'S OUTPUT GENERATION $$$$$$$$$$$$$$$$

-- #########################################################

out_proc : process(clk, rstn) is

begin

if rstn = '0' then



allow_SBA_int <='1';

GXTP_ranging_request_service <= '0';

BWmap_fifo_rd <= '0';

BWmap_valid <= '0';

BWmap_valid_int <= '0';

BWmap_data <= (others => '0');

BWmap_data_int <= (others => '0');

BWmap_onuid_int <= (others => '0');

BWmap_onuid <=(others =>'0');

zero_reg <= (others => '0');

BWmap_fifo_data_int <= (others => '0');

counter <= "000000000001";

deliver_last_word <='0';

single_word <='0';

BWmap_fifo_empty_d <='1';

fclk_d <='0';

elsif rising_edge(clk) then

BWmap_data <= BWmap_data_int ;

BWmap_valid <= BWmap_valid_int;

BWmap_onuid <= BWmap_onuid_int;

if fclk='1' then

if counter > "00000000001" then

counter<=counter-"00000000001";

else


counter<=regular_ranging_interval;

end if;


end if;
fclk_d<=fclk;

BWmap_fifo_empty_d<=BWmap_fifo_empty;

if current_state= PREPARE_RANGING then

if fclk_d='1' then

allow_SBA_int <='0';

elsif allow_sba_int='0' then

allow_sba_int<='0';

else


allow_sba_int<='1';

end if;


elsif current_state=silent1 then

allow_SBA_int <='0';

else

allow_SBA_int <='1';



end if;

if (current_state=NORMAL_DBA or current_state=AFTER_SILENT or current_state=PREPARE_RANGING) then

if current_normal_dba_state=idle or current_normal_dba_state=receive_header

or current_normal_dba_state=wait_fifo_data or current_normal_dba_state=close_delivery then

BWmap_valid_int<='0';

else


BWmap_valid_int<='1';

end if;


else

if current_init_state=close then

BWmap_valid_int<='1';

else


BWmap_valid_int<='0';

end if;


end if;

if spec_broad_request_int='1' and spec_broad_req_as_int=requested_rangingID then

GXTP_ranging_request_service<='1';

else


GXTP_ranging_request_service<='0';

end if;
---------------------- BW map delivery --------------------------------------------------

if current_normal_dba_state=deliver_header then

BWmap_data_int<= header;

BWmap_onuid_int <="00";

elsif current_normal_dba_state=deliver_word1 then

BWmap_data_int<= BWmap_fifo_data_int(63 downto 48);

BWmap_onuid_int<= BWmap_fifo_data_int(71 downto 70);

elsif current_normal_dba_state=deliver_word2 then

BWmap_data_int<= BWmap_fifo_data_int(47 downto 32);

BWmap_onuid_int<= BWmap_fifo_data_int(69 downto 68);

elsif current_normal_dba_state=deliver_word3 then

BWmap_data_int<= BWmap_fifo_data_int(31 downto 16);

BWmap_onuid_int<= BWmap_fifo_data_int(67 downto 66);

elsif current_normal_dba_state=deliver_word4 then

BWmap_data_int<= BWmap_fifo_data_int(15 downto 0);

BWmap_onuid_int<= BWmap_fifo_data_int(65 downto 64);

elsif current_state = silent1 or current_state = silent2 then -- or current_state = silent1 then ---

BWmap_data_int(14 downto 0)<=(others =>'0');

BWmap_onuid_int <="00";

if current_init_state=close then

BWmap_data_int(15)<='1';

else

BWmap_data_int(15)<='0';



end if;

else


BWmap_data_int<=zero_reg;

BWmap_onuid_int <="00";

end if;

if (current_normal_dba_state=deliver_word2 and deliver_last_word='0') or current_normal_dba_state=receive_header

then

BWmap_fifo_rd<='1';



else

BWmap_fifo_rd<='0';

end if;
if current_normal_dba_state=deliver_word4 and bwmap_fifo_empty='1' then

deliver_last_word<='1';

elsif current_normal_dba_state=idle then

deliver_last_word<='0';

end if;
if current_normal_dba_state=deliver_header and bwmap_fifo_empty='1' then

single_word<='1';

elsif current_normal_dba_state=idle then

single_word<='0';

end if;

if current_normal_dba_state= deliver_word4 or current_normal_dba_state= deliver_header then

BWmap_fifo_data_int <= BWmap_fifo_data;

end if;


end if; -- clk

end process out_proc;


------------------------------------------------------------------------

--------------------- normal DBA FSM -----------------------------------

--------------------------------------------------------------------------
normal_dba_proc : process(clk, rstn) is

begin


if rstn = '0' then

current_init_state<=idle1;

current_normal_dba_state <= idle;

elsif rising_edge(clk) then

current_normal_dba_state <= next_normal_dba_state;

current_init_state<=next_init_state;

end if;

end process normal_dba_proc;

---------------
normal_dba_fsm_proc : process(current_normal_dba_state, current_state, fclk ,BWmap_fifo_empty,

GXTP_ranging_request,BWmap_fifo_empty_d,deliver_last_word,single_word) is

begin

if current_state=normal_dba or current_state = prepare_ranging or current_state = after_silent then --- silent2 then ---



case current_normal_dba_state is

when idle =>

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