Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




старонка20/25
Дата канвертавання24.04.2016
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-- PLOAM = 13 bytes

-- PCBu = 2 bytes

-- FEC = 16 bytes

-- 2. PLOu is inserted when the Allocation Structures address AllocIDs of different ONUs.

-- 3.AllowSBA will be active at least for two fclk high periods.

-- 4.Spec_broad_req_valid is active at the begining of the frame that it has to be inserted.

-- BW map forwarder is responsible for that.

-- 5.Fclk and GBWstruct_valid rising edges should have a distance of 2 clock periods at least.

-- 6.AllowSBA and fclk falling edges should have a distance of 1 clock period.

-- 7. BWmap_header valid is activated at the begining (if fclk='1') of the

-- frame during which the corresponding BW will be delivered.

--

-- Design notes



-- 1. Client entities priority: ONU service, GBW_ts, SBW_ts

-- 2. The asp triggers the crc_insertion entity 3 clock periods after it has

-- received a "struct_valid" signal from gbw_ts, or sbw_ts or onu_service.

-- The crc_insertion cannot handle the access structure if they are

-- forwarded to it in less than 9 clock periods. For this reason, the last

-- process of the asp entity guarantees that the gbw_ts, sbw_ts and

-- onu_service will not deliver to the asp a new AllocId with less than 9

-- clock periods time distance. The ASP CONTROLS the CONSTRUCTION of ACCESS

-- STRUCTURES. It CONTSTRUCTS access structures for the assignment of both

-- GUARANTEED and SURPLUS bandwidth, as well as the assignment of OVERHEADS

-- and SN requests.

-----------------------------------------------------------------------------

-- Format of Access Structure

--

-- bits 12 12 16 16 8



-- ______________________________________

-- | AllocID | Flags| Start | Stop | CRC |

-- |__________|______|_ptr___|_ptr__|_____| Flags = PLSu(1) + PLOAM(1) + FEC(1) + PCBu(2) +

-- |63 52|51 40|39 24|23 8|7 0| AllocId preceded by PLOu(1)+ SNrequest (1)+ unassigned (1)+ NSR allocId (1)+ whole onu reporting AllocID (1)+ Rsv(2) = 12

--

-------------------------------------------------------------------



-- PCBu Mode

--00: Do not send PCBu at all.

--01: Send the 'mode 0' PCBu (two bytes).

--10: Send the 'mode 1' PCBu (three bytes).

--11: Send the 'mode 2' PCBu (five bytes).

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;
----------------------------

entity asp is

port(

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

fclk : in std_logic;

--gbw_ts i/f

GBWstruct_valid : in std_logic;

GBWstruct_allocid : in std_logic_vector(9 downto 0); --the allocID number

GBWonu_id : in std_logic_vector(7 downto 0); --the ONU_ID has to be received, as well

GBWalloc_bytes : in std_logic_vector(15 downto 0); --the number of bytes to be allocated/granted

GBWpcbu_fec : in std_logic_vector(5 downto 0); --whether we have FEC or PCBu ; 2 MSBs=PCBu, LSB=FEC

GBWplsu_ploam : in std_logic_vector(1 downto 0);

GBW_assigned : in std_logic; --guaranteed bandwidth has been assigned

GBW_ts_en : out std_logic; ------------------------enables the delivery of allocids from ts to asp -----added by nelly on 19/1103

--sbw_ts i/f

SBWstruct_valid : in std_logic;

SBWstruct_allocid : in std_logic_vector(9 downto 0); --the allocID number

SBWonu_id : in std_logic_vector(7 downto 0); --the ONU_ID has to be received, as well

SBWalloc_bytes : in std_logic_vector(15 downto 0); --the number of bytes to be allocated/granted

SBWpcbu_fec : in std_logic_vector(5 downto 0); --whether we have FEC or PCBu ; 2 MSBs=PCBu, LSB=FEC

SBWplsu_ploam : in std_logic_vector(1 downto 0);

--SBW_assigned : in std_logic; --surplus bandwidth has been assigned

SBW_ts_en : out std_logic; ------------------- active 1 -----enables the delivery of allocids from ts to asp


available_bytes:out std_logic_vector(14 downto 0);

--- onu_po i/f

ONU_po_struct_valid : in std_logic;

ONU_po_struct_allocID: in std_logic_vector(9 downto 0);

ONU_po_ONU_id : in std_logic_vector(7 downto 0);

ONU_po_alloc_bytes : in std_logic_vector(15 downto 0); --always (others => '0')

ONU_po_pcbu_fec : in std_logic_vector(2 downto 0); --Q: about FEC

ONU_po_plsu_ploam : in std_logic_vector(1 downto 0);

ONU_po_assigned : in std_logic; --ONU_po has finished po allocID, surplus follows

ONU_po_en : out std_logic; --from asp, indicating that the ONU_po will be pod

---------- i/f to BW map -----------------------------------

BWmap_header : out std_logic_vector(15 downto 0);

BWmap_header_valid : out std_logic;

allow_SBA : in std_logic; --'0' : disable surplus bw allocation

Spec_broad_req_allocid : in std_logic_vector(11 downto 0); --specific broadcast request

Spec_broad_req_FEC : in std_logic;

Spec_broad_req_PLSu : in std_logic;

Spec_broad_req_PLOAM : in std_logic;

Spec_broad_req_valid : in std_logic;

--crc insertion

BWmap_fifo_selection : out std_logic;

access_structure_valid : out std_logic;

access_structure : out std_logic_vector(71 downto 8)--(63 downto 8) --this is a 56-bit reg; crc=8 bits are to added afterwards

);


end; -- entity asp;

--------------------------------

architecture asp_b of asp is
type TStates is (WAITING_NEW_ALLOCID_st,

prepare_pointers,

prepare_spec_broad_req, PREPARE_ACCSTRUCT_st); -- WAIT_RESPONSE_st,

signal current_state, next_state : TStates;

subtype large_int is integer range 0 to 19450;

signal start_ptr, stop_ptr : large_int;

constant plou_con : integer := 15;

constant plsu_con : integer := 120;

constant ploam_con : integer := 13;

constant fec_con : integer := 16;

constant full_payload_con : integer := 256;

constant unassigned : std_logic_vector(9 downto 0):="0011111111";

signal Remaining_bytes : integer range 0 to 19450; --Total Allocation Bytes Integer

signal obt_ONU, cur_ONU : std_logic_vector(7 downto 0); --obtained and current ONU

signal struct_valid :std_logic;

signal access_structure_valid_int :std_logic;

signal onu_po_state :std_logic;

signal onu_po_state_d :std_logic;

signal gbw_state :std_logic;

signal gbw_state_d :std_logic;

signal onu_po_en_int :std_logic;

signal SBW_ts_en_int :std_logic;

signal gbw_ts_en_int :std_logic;

signal num_of_AS :integer range 0 to 1023;

signal Spec_broad_req_2binserted :std_logic;

signal BWmap_header_valid_int :std_logic;

signal bwmap_fifo_selection_int :std_logic;

signal onu_id :std_logic_vector(7 downto 0);

signal struct_allocid :std_logic_vector(9 downto 0);

signal alloc_bytes :std_logic_vector(15 downto 0);

signal pcbu_fec :std_logic_vector(5 downto 0);

signal plsu_ploam :std_logic_vector(1 downto 0);

signal diff_onu_s :std_logic;

signal access_structure_int : std_logic_vector(71 downto 8);

signal Spec_broad_req_allocid_int : std_logic_vector(11 downto 0); --specific broadcast request

signal Spec_broad_req_FEC_int : std_logic;

signal Spec_broad_req_PLSu_int : std_logic;

signal Spec_broad_req_PLOAM_int : std_logic;

signal fclk_d : std_logic;

signal wait_counter1 : integer range 0 to 7;

signal wait_counter2 : integer range 0 to 7;

-------------------------------------------------------------------------------

begin
BWmap_header_valid <=BWmap_header_valid_int;

bwmap_fifo_selection <=bwmap_fifo_selection_int;

access_structure(41 downto 40) <= "00";

-------------------------------------------------------------------------------

struct_valid<=GBWstruct_valid or SBWstruct_valid or onu_po_struct_valid;

available_bytes<=conv_std_logic_vector(Remaining_bytes, 15);

SBW_ts_en <=SBW_ts_en_int;

onu_po_en <=onu_po_en_int;


-----------------

process(clk, rstn)-- is

begin

if rstn = '0' then



current_state <= WAITING_NEW_ALLOCID_st;

elsif rising_edge(clk) then

current_state <= next_state;

end if;


end process;

---------------


process(current_state, struct_valid, spec_broad_req_2binserted )

begin
case current_state is

when WAITING_NEW_ALLOCID_st =>

if spec_broad_req_2binserted='1' then

next_state<=prepare_spec_broad_req;

elsif struct_valid = '1' then

next_state<=PREPARE_pointers;

else


next_state <= WAITING_NEW_ALLOCID_st;

end if;


when prepare_spec_broad_req =>

next_state<=PREPARE_ACCSTRUCT_st;

when prepare_pointers =>

next_state<=PREPARE_ACCSTRUCT_st;


when PREPARE_ACCSTRUCT_st =>

next_state <= WAITING_NEW_ALLOCID_st;

when others =>

next_state <= WAITING_NEW_ALLOCID_st;

end case;

end process;


---------------

process(clk, rstn) --is

begin

if rstn = '0' then


obt_ONU <= (others => '0'); --obtained ONU, that is the ONU that will be pod

cur_ONU <= (others => '1'); --current ONU is unassigned

Remaining_bytes <= 19440;

start_ptr <= 0;

stop_ptr <= 0;

access_structure_valid_int <= '0';

access_structure_valid <= '0';

access_structure_int <= (others => '0');

access_structure(71 downto 42) <= (others => '0');

access_structure(39 downto 8) <= (others => '0');

num_of_AS<=0;

diff_onu_s<='1';

bwmap_fifo_selection_int<='1';

elsif rising_edge(clk) then

access_structure_valid<=access_structure_valid_int;

access_structure(71 downto 42)<=access_structure_int(71 downto 42);

access_structure(39 downto 8) <=access_structure_int(39 downto 8);

access_structure_valid_int <= '0';


if current_state= WAITING_NEW_ALLOCID_st and struct_valid = '1' and onu_id /= cur_ONU then

diff_onu_s<='1';

elsif current_state= prepare_pointers then

diff_onu_s<='0';

end if;

case current_state is



when WAITING_NEW_ALLOCID_st =>
if struct_valid = '1' then

obt_ONU <= onu_id;

access_structure_int(71 downto 64) <= onu_id;

access_structure_int(63 downto 52) <= "00" & struct_allocid; --allocID

access_structure_int(49 downto 47) <= pcbu_fec(0) & pcbu_fec(2 downto 1); --PCBu & FEC

access_structure_int(44 downto 42) <=pcbu_fec(5 downto 3);

access_structure_int(45)<='0';

if num_of_as=0 then

stop_ptr <=stop_ptr+conv_integer(alloc_bytes)-1 ;

else


stop_ptr <=stop_ptr+conv_integer(alloc_bytes);

end if;


access_structure_int(51 downto 50) <= plsu_ploam;

elsif fclk='1' and allow_sba='1' then

stop_ptr<=0;

start_ptr<=0;

Remaining_bytes<=19440; --total allocated bytes = (initially) 19440

num_of_as<=0;

bwmap_fifo_selection_int<= not bwmap_fifo_selection_int;

end if;


when prepare_spec_broad_req =>
start_ptr<=15;

access_structure_int(46)<='1';

obt_onu<=conv_std_logic_vector(254, 8);

access_structure_int(71 downto 64)<=(others =>'0');

access_structure_int(63 downto 52) <= spec_broad_req_allocid_int; --allocID

access_structure_int(49)<=Spec_broad_req_FEC_int;

access_structure_int(48 downto 47) <= "00"; -----pcbu_fec & pcbu_fec(2 downto 1); --PCBu & FEC

access_structure_int(45)<='1';

access_structure_int(44 downto 42) <="000";

access_structure_int(51)<=Spec_broad_req_PLSu_int;

access_structure_int(50)<=Spec_broad_req_PLOAM_int;

if Spec_broad_req_FEC_int='0' then

if Spec_broad_req_PLOAM_int='1' then

if Spec_broad_req_PLSu_int='1' then

stop_ptr<=PLSu_con+PlOAM_con+14;

else


stop_ptr<=PLOAM_con+14;

end if;


else

if Spec_broad_req_PLSu_int='1' then

stop_ptr<=PLSu_con+14;

else


stop_ptr<=15;

end if;


end if;

else -- FEC ='1'

if Spec_broad_req_PLOAM_int='1' then

if Spec_broad_req_PLSu_int='1' then

stop_ptr<=PLSu_con+PlOAM_con+30;

else


stop_ptr<=PLOAM_con+30;

end if;


else

if Spec_broad_req_PLSu_int='1' then

stop_ptr<=PLSu_con+30;

else


stop_ptr<=31;

end if;


end if;

end if;

when prepare_pointers =>

if num_of_as=0 then

start_ptr <= start_ptr+15;

access_structure_int(46)<='1';

else

if diff_onu_s='1' then



start_ptr <= start_ptr+16;

access_structure_int(46)<='1';

else

start_ptr <= start_ptr + 1;



access_structure_int(46)<='0';

end if;


end if;

if diff_onu_s ='1' or num_of_as=0 then

stop_ptr<=stop_ptr+15;

end if;


when PREPARE_ACCSTRUCT_st =>

cur_ONU <= obt_ONU;

access_structure_valid_int <= '1';

access_structure_int(39 downto 24) <= conv_std_logic_vector(start_ptr,16);

access_structure_int(23 downto 8) <= conv_std_logic_vector(stop_ptr,16);

Remaining_bytes <= 19440-stop_ptr;

num_of_as <= num_of_as+1;

start_ptr <=stop_ptr;

when others =>

null;


end case;

end if; -- clk

end process;
-----------------

process(clk, rstn)-- is

begin

if rstn = '0' then



Spec_broad_req_2binserted<='0';

Spec_broad_req_allocid_int<=(others =>'0');

Spec_broad_req_FEC_int <= '0';

Spec_broad_req_PLSu_int <='0';

Spec_broad_req_PLOAM_int <='0';

elsif rising_edge(clk) then


if Spec_broad_req_valid='1' then

Spec_broad_req_2binserted<='1';

elsif current_state=prepare_spec_broad_req then

Spec_broad_req_2binserted<='0';

end if;
if Spec_broad_req_valid='1' then

Spec_broad_req_allocid_int<= Spec_broad_req_allocid;

Spec_broad_req_FEC_int <= Spec_broad_req_FEC;

Spec_broad_req_PLSu_int <= Spec_broad_req_PLSu;

Spec_broad_req_PLOAM_int <= Spec_broad_req_PLOAM;

end if;


end if;

end process;


------------------------------------------------------

-------------- header preparation -------------------

------------------------------------------------------

BWmap_header(13 downto 10)<="0000";


process(clk, rstn) --is

begin


if rstn = '0' then

BWmap_header_valid_int<='0';

BWmap_header (15 downto 14)<=(others =>'0');

BWmap_header(9 downto 0) <=(others =>'0');

elsif rising_edge(clk) then

if current_state=WAITING_NEW_ALLOCID_st and fclk='1' and allow_sba='1' then

BWmap_header_valid_int<='1';

BWmap_header(9 downto 0)<=conv_std_logic_vector(num_of_as,10);

else

BWmap_header_valid_int<='0';



end if;

if gbwstruct_valid='1' and gbwstruct_allocID=unassigned then

BWmap_header(14)<='1' ;

elsif BWmap_header_valid_int='1' then

BWmap_header(14)<='0' ;

end if;


if current_state=prepare_spec_broad_req then

BWmap_header(15)<= '1';

elsif BWmap_header_valid_int='1' then

BWmap_header(15)<='0' ;

end if;

end if;


end process;

mux: process(gBW_ts_en_int,onu_po_en_int,

gbwonu_id, gbwstruct_allocid, gbwalloc_bytes, gbwpcbu_fec, GBWplsu_ploam,

onu_po_onu_id, onu_po_struct_allocid, onu_po_alloc_bytes, onu_po_pcbu_fec, onu_po_plsu_ploam,

sbwonu_id, sbwstruct_allocid, sbwalloc_bytes , sbwpcbu_fec, sbwplsu_ploam)

begin
if gBW_ts_en_int = '1' then

onu_id <=gbwonu_id;

struct_allocid<=gbwstruct_allocid;

alloc_bytes <=gbwalloc_bytes;

pcbu_fec <=gbwpcbu_fec;

plsu_ploam <=GBWplsu_ploam;

elsif onu_po_en_int = '1' then

onu_id <=onu_po_onu_id;

struct_allocid<=onu_po_struct_allocid;

alloc_bytes <=onu_po_alloc_bytes;

pcbu_fec (2 downto 0)<=onu_po_pcbu_fec;

pcbu_fec (5 downto 3)<="000";

plsu_ploam <=onu_po_plsu_ploam;

else

onu_id <=sbwonu_id;



struct_allocid<=sbwstruct_allocid;

alloc_bytes <=sbwalloc_bytes;

pcbu_fec <=sbwpcbu_fec;

plsu_ploam <=sbwplsu_ploam;

end if;

end process;


---------------------------

------------- switch over gbw, onu_po and sbw -------------------

process(clk, rstn) --is

begin


if rstn = '0' then

onu_po_en_int <= '0';

SBW_ts_en_int <= '0';

gbw_ts_en_int <= '0';

onu_po_state<='0';

onu_po_state_d<='0';

gbw_state<='0';

gbw_state_d<='0';

gbw_ts_en<='0';

fclk_d<='0';

wait_counter1<=0;

wait_counter2<=0;


elsif rising_edge(clk) then

fclk_d<=fclk;


------------ ONU po --------------------------------

if (current_state= WAITING_NEW_ALLOCID_st or current_state= PREPARE_ACCSTRUCT_st )and onu_po_state ='1' then

onu_po_en_int <= '1';

else


onu_po_en_int <= '0';

end if;


--if fclk='1' then

if (fclk_d='1' and Spec_broad_req_valid='0') or wait_counter1=7 then -- check the correct value

onu_po_state<='1';

elsif onu_po_assigned='1' then

onu_po_state<='0';

end if;


onu_po_sTATE_d<=onu_po_state;

if (fclk_d='1' and Spec_broad_req_valid='1') then

wait_counter1<=1;

elsif wait_counter1<7 and wait_counter1>0 then

wait_counter1<=wait_counter1+1;

elsif wait_counter1=7 then

wait_counter1<=0;

end if;


-----------------------------------------------------
------------ gbw ts -------------------------

if onu_po_state='0' and onu_po_state_d='1' then

gbw_state<='1';

elsif GBW_assigned='1' then

gbw_state<='0';

end if;


gbw_state_d<=gbw_state;
if gbw_state_d='0' and gbw_state='1' then

gbw_ts_en<='1';

else

gbw_ts_en<='0';



end if;

if gbw_state='1' and current_state = WAITING_NEW_ALLOCID_st then

gbw_ts_en_int <= '1';

else


gbw_ts_en_int <= '0';

end if;


-----------------------------------------------------

------------ sbw ts --------------------------------

--if gbw_assigned='1' then

if wait_counter2=6 and allow_sba='1' then

sbw_ts_en_int<='1';

else


sbw_ts_en_int<='0';

end if;


if gbw_assigned='1' then

wait_counter2<=1;

elsif wait_counter2<6 and wait_counter2>0 then

wait_counter2<=wait_counter2+1;

elsif wait_counter2=6 then

wait_counter2<=0;

end if;

end if; -- clk

end process;
end ; --architecture asp_a;

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-------------------------------------------

--------------------------------------------------------------------

-- Design Unit Name : CRC_insertion

-- Purpose : This entity receives the 7 bytes of the Allocation structure from

-- the ASP and calculates the CRC 8. The resulting Allocation Structure is

-- written to a FIFO.

--


-- File Name : CRC_insertion.vhd

--------------------------------------------------------------------

-- --------------------------------------------------------------------------

-- A S S U M P T I O N

-- 1. Two consecutive rising edges of the Access Structure Valid signal from

-- the ASP will have a time distance of 9 clock periods.

-------------------------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


----------------------------

entity CRC_insertion is

port(

clk : in std_logic; --FPGA's clock



rstn : in std_logic;

--BWmap fifo i/f

BWmap_fifo_wr :out std_logic;

BWmap_fifo_data :out std_logic_vector(71 downto 0);

--access structure

access_structure_valid : in std_logic;

access_structure : in std_logic_vector(71 downto 8) --this is a 56-bit reg; crc=8 bits are to added afterwards

);


end; -- entity CRC_insertion;

--------------------------------

architecture CRC_insertion_b of CRC_insertion is
component CRC8 is
port(CRC8_clk : in std_logic;

CRC8_resetn : in std_logic;

CRC8_data_i : in std_logic_vector(7 downto 0);

CRC8_data_vld_i : in std_logic;

CRC8_data_o : out std_logic_vector(7 downto 0);

CRC8_data_vld_o : out std_logic

);
end component;
type TStates is (idle,

add_word1, add_word2,

add_word3, add_word4,

add_word5, add_word6,

add_word7,

receive_crc, write_fifo);


signal current_state, next_state : TStates;

signal CRC_input_valid :std_logic;

signal CRC_input_data : std_logic_vector(7 downto 0);

signal CRC_output : std_logic_vector(7 downto 0);

signal CRC_output_valid : std_logic;

signal access_structure_int_reg : std_logic_vector(55 downto 8);

signal CRC_rst : std_logic;
------------------------------------------------------------------------------

begin


CRC_module: CRC8
port map (CRC8_clk =>clk, -- : in std_logic;

CRC8_resetn =>CRC_rst, -- : in std_logic;

CRC8_data_i => CRC_input_data, -- : in std_logic_vector(7 downto 0);

CRC8_data_vld_i =>CRC_input_valid , --: in std_logic;

CRC8_data_o =>CRC_output, --: out std_logic_vector(7 downto 0);

CRC8_data_vld_o =>CRC_output_valid --: out std_logic

);
-----------------

process(clk, rstn)-- is

begin

if rstn = '0' then



current_state <= idle;

elsif rising_edge(clk) then

current_state <= next_state;

end if;


end process;

---------------


process(current_state, access_structure_valid)

begin
case current_state is

when idle =>

if access_structure_valid='1' then

next_state<=add_word1;

else


next_state <= idle;

end if;


when add_word1=>

next_state<=add_word2;

when add_word2=>

next_state<=add_word3;

when add_word3=>

next_state<=add_word4;

when add_word4=>

next_state<=add_word5;

when add_word5=>

next_state<=add_word6;

when add_word6=>

next_state<=add_word7;

when add_word7=>

next_state<=receive_crc;

when receive_crc=>

next_state<=write_fifo;

when write_fifo =>

if access_structure_valid='1' then

next_state<=add_word1;

else


next_state <= idle;

end if;


end case;

end process;


---------------

process(clk, rstn) --is

begin

if rstn = '0' then



CRC_input_valid <='0';

BWmap_fifo_wr <='0';

BWmap_fifo_data <=(others =>'0');

access_structure_int_reg <=(others =>'0');

CRC_input_data <=(others =>'0');

CRC_rst <='0';

elsif rising_edge(clk) then

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