Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




старонка19/25
Дата канвертавання24.04.2016
Памер2.32 Mb.
1   ...   15   16   17   18   19   20   21   22   ...   25

);

end entity update_reqmat;



architecture struct of update_reqmat is
type SStates is (wait_for_activation,

wait_for_read_ack,

wait_for_write_ack,

tc_read,


wait_dbarx,

tc_write,

wait_for_tc_ack);

signal current_state : SStates;

signal AllocID_s : std_logic_vector (9 downto 0);

signal flag_data_i : std_logic_vector (15 downto 0);

signal flag_selection_int : std_logic;

signal flag_data_in : std_logic_vector (15 downto 0);

signal req_data_out_int : std_logic_vector (20 downto 0);

signal tcont : std_logic_vector (2 downto 0);

begin
flag_selection <= flag_selection_int;

flag_data_out <= flag_data_i;

req_addr <= AllocID_s;
comb_proc: process (flag_selection_int, flag4_data_in, flag3_data_in)

begin


if flag_selection_int='1' then

flag_data_in<=flag4_data_in;

else

flag_data_in<=flag3_data_in;



end if;

end process;


asp2reqmat_proc: process (rstn, clk) is

begin
if rstn = '0' then

current_state <= wait_for_activation;

req_cs <= '0';

req_we <= '0';

req_data_out <= (others => '0');

req_data_out_int <= (others => '0');

AllocID_s <= (others => '0');

flag_cs <= '0';

flag_we <= '0';

flag_selection_int <='0';

flag_data_i <= (others => '0');

tcont <= (others => '0');

flag_addr<=(others =>'0');


elsif rising_edge(clk) then
case current_state is

when wait_for_activation =>

req_cs <= '0';

req_we <= '0'; --Read Request Matrix

if gbw_valid = '1' then

AllocID_s <= gbw_allocID;

req_data_out_int <= gbw_req_data_in - gbw_allocation_bytes;

tcont <=gbw_tcont;

if (gbw_tcont = "011") then -- T-CONT 3

flag_selection_int <= '0';

else

flag_selection_int <= '1';



end if;

current_state <= wait_for_read_ack;

elsif sbw_valid = '1' then

AllocID_s <= sbw_allocID;

tcont <=sbw_tcont;

if (sbw_tcont = "011") then -- T-CONT 3

flag_selection_int <= '0';

else


flag_selection_int <= '1';

end if;


current_state <= wait_for_read_ack;

req_data_out_int <= sbw_req_data_in - sbw_allocation_bytes;

end if;

if gbw_valid = '1' then



flag_addr<=gbw_allocID(9 downto 4);

elsif sbw_valid = '1' then

flag_addr<=sbw_allocID(9 downto 4);

else


flag_addr<=(others =>'0');

end if;


when wait_for_read_ack =>

req_data_out<=req_data_out_int;

flag_we <= '0';

req_cs <= '1';

req_we <= '1';

if req_data_out_int = "000000000000000000000" then --reset flag

if (tcont = "011") then -- T-CONT 3

if dbarx_flag_selection= '0' and dbarx_flag_addr="000000" then

flag_cs <= '1';

current_state <= tc_read;

flag_addr <= AllocID_s(9 downto 4);

else


current_state<=wait_dbarx;

end if;
elsif (tcont = "000") then -- T-CONT 4

if dbarx_flag_selection= '1' and dbarx_flag_addr="000000" then

flag_cs <= '1';

current_state <= tc_read;

flag_addr <= AllocID_s(9 downto 4);

else

current_state<=wait_dbarx;



end if;

else -- T-CONT 2

flag_cs <= '0';

current_state <= wait_for_write_ack;

flag_addr<=(others =>'0');

end if;


else -- non zero request

flag_cs <= '0';

flag_selection_int <= '0';

current_state <= wait_for_write_ack;

flag_addr<=(others =>'0');

end if;


when wait_dbarx =>

req_cs <= '0';

req_we <= '0';

if dbarx_flag_addr="000000" then

flag_cs <= '1';

current_state <= tc_read;

flag_addr <= AllocID_s(9 downto 4);

else


current_state <=wait_dbarx;

end if;


when wait_for_write_ack =>

req_cs <= '0';

req_we <= '0';

if req_ack = '1' then

req_data_out <= (others => '0');

current_state <= wait_for_activation;

end if;

when tc_read =>



req_cs <= '0';

flag_cs <= '0';

req_we <= '0';

if flag_ack = '1' then

flag_data_i <= flag_data_in;

current_state <= tc_write;

end if;

when tc_write =>



flag_cs <= '1';

flag_we <= '1';

flag_data_i(conv_integer(AllocID_s (3 downto 0))) <= '0';

current_state <= wait_for_tc_ack;

when wait_for_tc_ack =>

flag_we <= '0';

flag_cs <= '0';

flag_addr<=(others =>'0');

current_state <= wait_for_activation;

end case;

end if;
end process;

------------------------

end architecture struct;

--------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--


-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"

-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --

-- FOR A PARTICULAR PURPOSE.

--


-- Xilinx products are not intended for use in life support

-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--


-- (c) Copyright 1995-2003 Xilinx, Inc.

-- All rights reserved.

------------------------------------------------------------------------------

-- You must compile the wrapper file flags_mem.vhd when simulating

-- the core, flags_mem. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Guide".
-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY flags_mem IS

port (

addr: IN std_logic_VECTOR(5 downto 0);



clk: IN std_logic;

din: IN std_logic_VECTOR(15 downto 0);

dout: OUT std_logic_VECTOR(15 downto 0);

en: IN std_logic;

we: IN std_logic);

END flags_mem;


ARCHITECTURE flags_mem_a OF flags_mem IS
component wrapped_flags_mem

port (


addr: IN std_logic_VECTOR(5 downto 0);

clk: IN std_logic;

din: IN std_logic_VECTOR(15 downto 0);

dout: OUT std_logic_VECTOR(15 downto 0);

en: IN std_logic;

we: IN std_logic);

end component;
-- Configuration specification

for all : wrapped_flags_mem use entity XilinxCoreLib.blkmemsp_v5_0(behavioral)


generic map(

c_sinit_value => "0",

c_reg_inputs => 0,

c_yclk_is_rising => 1,

c_has_en => 1,

c_ysinit_is_high => 1,

c_ywe_is_high => 1,

c_ytop_addr => "1024",

c_yprimitive_type => "16kx1",

c_yhierarchy => "hierarchy1",

c_has_rdy => 0,

c_has_limit_data_pitch => 0,

c_write_mode => 0,

c_width => 16,

c_yuse_single_primitive => 0,

c_has_nd => 0,

c_enable_rlocs => 0,

c_has_we => 1,

c_has_rfd => 0,

c_has_din => 1,

c_ybottom_addr => "0",

c_pipe_stages => 0,

c_yen_is_high => 1,

c_depth => 64,

c_has_default_data => 1,

c_limit_data_pitch => 18,

c_has_sinit => 0,

c_mem_init_file => "mif_file_16_1",

c_default_data => "0",

c_ymake_bmm => 0,

c_addr_width => 6);

BEGIN
U0 : wrapped_flags_mem

port map (

addr => addr,

clk => clk,

din => din,

dout => dout,

en => en,

we => we);

END flags_mem_a;


-- synopsys translate_on

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 12/9/03

-------------------------------------------

-- Design Unit Name : Update ReqMat

-- Purpose : Updates the Request Matrix after request of the gbw_ts or the sbw_ts.

-- File Name : update_reqmat.vhd

---------------------------------------------

-- Description ----------------------------

-- 1. It receives as input from gbwts or sbwts the allocID, valid,

-- gbw_allocation_bytes_bytes req_data_in (the request number) and the

-- tcont. Hence its responsibility is to write in the request matrix the

-- value req_data_in - allocation bytes. In case that the Tcont is 3 or 4

-- and the req_data_in equals the allocation bytes, the respective flag is

-- reset.

-----------------------------------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


entity update_reqmat is

port (


clk :in std_logic;

rstn : in std_logic;

--gbwts i/f

gbw_valid : in std_logic;

gbw_allocID : in std_logic_vector (9 downto 0);

gbw_allocation_bytes : in std_logic_vector (15 downto 0);

gbw_req_data_in : in std_logic_vector(20 downto 0);

gbw_tcont : in std_logic_vector (2 downto 0); --3bits tcont_type

--sbwts i/f

sbw_valid : in std_logic;

sbw_allocID : in std_logic_vector (9 downto 0);

sbw_allocation_bytes : in std_logic_vector (15 downto 0);

sbw_req_data_in : in std_logic_vector(20 downto 0);

sbw_tcont : in std_logic_vector (2 downto 0); --3bits tcont_type

-- Signals for Request Matrix ------------------

req_cs : out std_logic;

req_we : out std_logic;

req_ack : in std_logic;

req_addr : out std_logic_vector(9 downto 0); --Idio me tou AllocID

req_data_out : out std_logic_vector(20 downto 0);

---- dba_rx i/f

dbarx_flag_selection : in std_logic;

dbarx_flag_addr : in std_logic_vector(5 downto 0);

--tcont3/tcont4 regions i/f

flag_cs : out std_logic;

flag_we : out std_logic;

flag_ack : in std_logic;

flag_selection : out std_logic;

flag_addr : out std_logic_vector(5 downto 0);

flag_data_out : out std_logic_vector (15 downto 0);

flag3_data_in : in std_logic_vector (15 downto 0);

flag4_data_in : in std_logic_vector (15 downto 0)

);

end entity update_reqmat;



architecture struct of update_reqmat is
type SStates is (wait_for_activation,

wait_for_read_ack,

wait_for_write_ack,

tc_read,


wait_dbarx,

tc_write,

wait_for_tc_ack);

signal current_state : SStates;

signal AllocID_s : std_logic_vector (9 downto 0);

signal flag_data_i : std_logic_vector (15 downto 0);

signal flag_selection_int : std_logic;

signal flag_data_in : std_logic_vector (15 downto 0);

signal req_data_out_int : std_logic_vector (20 downto 0);

signal tcont : std_logic_vector (2 downto 0);

begin
flag_selection <= flag_selection_int;

flag_data_out <= flag_data_i;

req_addr <= AllocID_s;
comb_proc: process (flag_selection_int, flag4_data_in, flag3_data_in)

begin


if flag_selection_int='1' then

flag_data_in<=flag4_data_in;

else

flag_data_in<=flag3_data_in;



end if;

end process;


asp2reqmat_proc: process (rstn, clk) is

begin


if rstn = '0' then

current_state <= wait_for_activation;

req_cs <= '0';

req_we <= '0';

req_data_out <= (others => '0');

req_data_out_int <= (others => '0');

AllocID_s <= (others => '0');

flag_cs <= '0';

flag_we <= '0';

flag_selection_int <='0';

flag_data_i <= (others => '0');

tcont <= (others => '0');

flag_addr<=(others =>'0');

elsif rising_edge(clk) then


case current_state is

when wait_for_activation =>

req_cs <= '0';

req_we <= '0'; --Read Request Matrix

if gbw_valid = '1' then

AllocID_s <= gbw_allocID;

req_data_out_int <= gbw_req_data_in - gbw_allocation_bytes;

tcont <=gbw_tcont;

if (gbw_tcont = "011") then -- T-CONT 3

flag_selection_int <= '0';

else

flag_selection_int <= '1';



end if;

current_state <= wait_for_read_ack;

elsif sbw_valid = '1' then

AllocID_s <= sbw_allocID;

tcont <=sbw_tcont;

if (sbw_tcont = "011") then -- T-CONT 3

flag_selection_int <= '0';

else


flag_selection_int <= '1';

end if;


current_state <= wait_for_read_ack;

req_data_out_int <= sbw_req_data_in - sbw_allocation_bytes;

end if;

if gbw_valid = '1' then



flag_addr<=gbw_allocID(9 downto 4);

elsif sbw_valid = '1' then

flag_addr<=sbw_allocID(9 downto 4);

else


flag_addr<=(others =>'0');

end if;


when wait_for_read_ack =>

req_data_out<=req_data_out_int;

flag_we <= '0';

req_cs <= '1';

req_we <= '1';

if req_data_out_int = "000000000000000000000" then --reset flag

if (tcont = "011") then -- T-CONT 3

if dbarx_flag_selection= '0' and dbarx_flag_addr="000000" then

flag_cs <= '1';

current_state <= tc_read;

flag_addr <= AllocID_s(9 downto 4);

else


current_state<=wait_dbarx;

end if;
elsif (tcont = "000") then -- T-CONT 4

if dbarx_flag_selection= '1' and dbarx_flag_addr="000000" then

flag_cs <= '1';

current_state <= tc_read;

flag_addr <= AllocID_s(9 downto 4);

else

current_state<=wait_dbarx;



end if;

else -- T-CONT 2

flag_cs <= '0';

current_state <= wait_for_write_ack;

flag_addr<=(others =>'0');

end if;


else -- non zero request

flag_cs <= '0';

flag_selection_int <= '0';

current_state <= wait_for_write_ack;

flag_addr<=(others =>'0');

end if;


when wait_dbarx =>

req_cs <= '0';

req_we <= '0';

if dbarx_flag_addr="000000" then

flag_cs <= '1';

current_state <= tc_read;

flag_addr <= AllocID_s(9 downto 4);

else


current_state <=wait_dbarx;

end if;


when wait_for_write_ack =>

req_cs <= '0';

req_we <= '0';

if req_ack = '1' then

req_data_out <= (others => '0');

current_state <= wait_for_activation;

end if;

when tc_read =>



req_cs <= '0';

flag_cs <= '0';

req_we <= '0';

if flag_ack = '1' then

flag_data_i <= flag_data_in;

current_state <= tc_write;

end if;

when tc_write =>



flag_cs <= '1';

flag_we <= '1';

flag_data_i(conv_integer(AllocID_s (3 downto 0))) <= '0';

current_state <= wait_for_tc_ack;

when wait_for_tc_ack =>

flag_we <= '0';

flag_cs <= '0';

flag_addr<=(others =>'0');

current_state <= wait_for_activation;

end case;

end if;
end process;

------------------------

end architecture struct;

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Design Unit Name : GXTP_sif

-- Purpose : Forwards the requests received through the serial interface from

-- the GLTP2 to the responsible entities.

-------------------------------------------------------------------------------

-- File Name : gxtp_sif_040206.vhd

-------------------------------------------------------------------------------

-- Assumptions:

-- On the SIF interface: Explicit reqs for PLSu and PLOAM signals are assumed

-- active high until GXTP_SIF_req_serviced is activated


library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


----------------------------

entity GXTP_sif is

port( clk : in std_logic; --FPGA's clock

rstn : in std_logic;

-------GXTP SIF signals -----------------

GXTP_sif_data : in std_logic;

--------- to whom it may concern --------------

GXTP_ranging_request :out std_logic;

GXTP_ranging_ID :out std_logic_vector(11 downto 0);

GXTP_ranging_PLSu_PLOAM :out std_logic_vector(1 downto 0);

GXTP_ranging_request_service :in std_logic;

-------- ONU_service interface -----------------------------

GXTP_SIF_onuid :out std_logic_vector(7 downto 0);

Explicit_PLOAM_req :out std_logic; ----- assumed active high until GXTP_SIF_req_serviced is activated

Explicit_PLSu_req :out std_logic;----- assumed active high until GXTP_SIF_req_serviced is activated

GXTP_SIF_req_serviced :in std_logic

);

end entity GXTP_sif;



--------------------------------

architecture GXTP_sif_a of GXTP_sif is


signal start_counter : std_logic;

signal ranging_request_s : std_logic;

signal PLOAM_request_s : std_logic;

signal PLSu_request_s : std_logic;

signal AllocID : std_logic_vector(11 downto 0);

signal Explicit_PLOAM_req_i : std_logic;

signal Explicit_PLSu_req_i : std_logic;

signal position_counter : integer range 0 to 16;

signal GXTP_data_sync : std_logic;

signal GXTP_data_int : std_logic;

signal GXTP_data_in_d : std_logic;

signal GXTP_ranging_request_i : std_logic;

constant number_of_positions : integer :=16;
begin
process(clk, rstn) is

begin


if rstn = '0' then

start_counter<='0';

position_counter<=0;

ranging_request_s<='0';

PLOAM_request_s <= '0';

PLSu_request_s<='0';

AllocID<=(others =>'0');

elsif rising_edge(clk) then


-------auxiliary signals -----------------

if GXTP_data_int='1' and position_counter=0 then

start_counter<='1';

elsif position_counter = number_of_positions then

start_counter<='0';

end if;


if position_counter = number_of_positions then

position_counter <= 0;

elsif position_counter > 0 or start_counter = '1' then

position_counter <= position_counter + 1;

end if;

----- Serial to Parallel ---------------------



case position_counter is

when 1 =>

ranging_request_s <= GXTP_data_in_d;

when 3 =>

PLOAM_request_s <= GXTP_data_in_d;

when 4 =>

PLSu_request_s <= GXTP_data_in_d;

when 5 to 16 =>

AllocID(16 - position_counter) <= GXTP_data_in_d;

when others =>

null;

end case;



-----------------------------------------------

end if;


end process;
GXTP_ranging_ID<=AllocID;

GXTP_ranging_request<=GXTP_ranging_request_i;


-----------------

process(clk, rstn) is

begin

if rstn = '0' then



GXTP_ranging_request_i <='0';

GXTP_SIF_onuid <=(others =>'0');

Explicit_PLOAM_req <='0';

Explicit_PLOAM_req_i <='0';

Explicit_PLSu_req <='0';

GXTP_ranging_PLSu_PLOAM <=(others =>'0');

Explicit_PLSu_req_i<='0';

elsif rising_edge(clk) then


if GXTP_ranging_request_service='1' then

GXTP_ranging_request_i<='0';

elsif position_counter = 16 then

if GXTP_ranging_request_i='0' then

GXTP_ranging_request_i<=ranging_request_s;

end if;


GXTP_ranging_PLSu_PLOAM(1)<=PLOAM_request_s;

GXTP_ranging_PLSu_PLOAM(0)<= PLSu_request_s ;

end if;

GXTP_SIF_onuid <=allocID(7 downto 0);



if GXTP_SIF_req_serviced='1' then

Explicit_PLOAM_req_i<='0';

elsif position_counter = 16 and ranging_request_s='0' then

Explicit_PLOAM_req_i<=PLOAM_request_s;

end if;

Explicit_PLOAM_req<=Explicit_PLOAM_req_i ;



if GXTP_SIF_req_serviced='1' then

Explicit_PLSu_req_i<='0';

elsif position_counter = 16 and ranging_request_s='0' then

Explicit_PLSu_req_i<=PLSu_request_s;

end if;

Explicit_PLSu_req<=Explicit_PLSu_req_i;



end if;

end process;


------------------------------------------------------------------------------

-----------------------------Synchronize MAC_clk with SPI_clk-----------------

------------------------------------------------------------------------------

syncrhonize_sif_2_clk : process (clk,rstn) is

begin

if (rstn = '0') then



GXTP_data_sync <= '0';

GXTP_data_int <= '0';

GXTP_data_in_d <='0';

elsif rising_edge(clk) then

GXTP_data_sync <= GXTP_sif_data;--GXTP_sif_data_d;

GXTP_data_int <= GXTP_data_sync;

GXTP_data_in_d <= GXTP_data_int;

end if;


end process;
-------------------------------------------------------------------------------

end architecture GXTP_sif_a;

-------------------------------------------

-- GIANT Project

-- NTUA

-------------------------------------------

--------------------------------------------------------------------

-- Design Unit Name : asp (Access Structure Preparation)

-- File Name : asp.vhd

--

-- Purpose/Descritpion : This entity receives the AllocID, the bytes that



-- should be granted to it and the flags (FEC, DBRu, e.t.c.) from the

-- GBW_TS, SBW_ts and ONU_service entities calculates the start and stop

-- pointers. After calculating the pointers it forwards the 7 (out of 8)

-- bytes of the Allocation structure (except the CRC field) along with the

-- ONUid to the CRC_insertion entity. It also inserts the specific

-- broadcast request access structures when notified by the BWmap forwarder

-- entity.

-- Note:

-- 1. ONU_service entity also notifies the current entity when a PLSu

-- or PLOAM overhead has to be granted even though dedicated access structure.

-- 2. The NSR, PLOu, WholeONU_dba_report, Unassigned and SN request

-- flags are also inserted.

--------------------------------------------------------------------

-- Assumptions

-- 1. PLOu = 15 bytes

-- PLSu = 120 bytes

1   ...   15   16   17   18   19   20   21   22   ...   25


База данных защищена авторским правом ©shkola.of.by 2016
звярнуцца да адміністрацыі

    Галоўная старонка