Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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inspection_completed : in std_logic; --inspection_completed

stall_inspection : out std_logic;

--bap & reqmat access

mem_req : out std_logic; --a request to bap_arbiter & reqmat_arbiter in the same time

mem_addr : out std_logic_vector(9 downto 0);


--bap i/f

bap_we : out std_logic;

bap_valid : in std_logic;

bap_param : in std_logic_vector(47 downto 0);


--reqmat i/f

reqmat_we : out std_logic;

reqmat_valid : in std_logic;

reqmat_param : in std_logic_vector(20 downto 0);


------ to update reqmat ----------------------------

allocation_bytes :out std_logic_vector(15 downto 0);

update_reqmat_cmd :out std_logic;

request :out std_logic_vector(20 downto 0);

t_cont :out std_logic_vector(1 downto 0);

--asp i/f

Available_bytes : in std_logic_vector(14 downto 0);

SBWstruct_RDY : out std_logic; --this signal serves as an allocid_valid and as RDY signal

SBWstruct_allocid : out std_logic_vector(9 downto 0);

SBWonu_id : out std_logic_vector(7 downto 0);

SBWalloc_bytes : out std_logic_vector(15 downto 0);

SBWpcbu_fec : out std_logic_vector(5 downto 0); -- Unassigned (1) + NSR(1) + Whole ONU reports (1) + reporting mode(2) + FEC(1

SBWplsu_PLOAM : out std_logic_vector(1 downto 0)

);


end entity sbw_ts;

---------------------------------

architecture sbw_ts_a of sbw_ts is
type TStates is (IDLE,

WAIT_SURPLUS_EN,

wait_sbwti_valid,

MEMORY_ACCESS,

preliminary_calculations,

PREPARE_SBWStruct,

deliver_SBWstruct,

wait_new_frame,

close_SBW

);

signal current_state, next_state : TStates;


constant NSR_fixed_allocation : std_logic_vector(15 downto 0) := X"0040";

constant FEC_NSR_fixed_allocation : std_logic_vector(15 downto 0) := X"0050";

constant PLSu_length : std_logic_vector(15 downto 0) := X"0078";

constant PLOAM_length : std_logic_vector(15 downto 0) := X"000D";

constant DBRu_length : std_logic_vector(15 downto 0) := X"0002";

constant fixed_difference :integer range 0 to 127 :=15;

constant minimum_surplus_allocation:integer range 0 to 2047 :=128;

signal allocid_reg : std_logic_vector(9 downto 0); --from timer_inspection

signal bap_param_reg : std_logic_vector(28 downto 0); --the width is not as long as bap info, since min TB info is not needed

signal reqmat_param_reg : std_logic_vector(20 downto 0);

signal available_bytes_int :std_logic_vector(15 downto 0);

signal bap_valid_flag, reqmat_valid_flag : std_logic;

signal SBWAlloc_bytes_int : std_logic_vector(15 downto 0);

signal NSR : std_logic;

signal fec_enabled : std_logic;

signal pbrep : std_logic; --piggy backed report

begin
request <=reqmat_param_reg;

SBWplsu_PLOAM <= "00";

SBWpcbu_fec(5)<='0';

SBWpcbu_fec(3)<='0';

SBWonu_id (7 )<='0';

SBWAlloc_bytes<=SBWAlloc_bytes_int;

reqmat_we <= '0';

bap_we <= '0';

-------------------------------------------------------

------------ FSM --------------------------------

process(clk, rstn)

begin


if rstn = '0' then

current_state <= IDLE;

elsif rising_edge(clk) then

current_state <= next_state;

end if;

end process;



--

process(current_state, fclk, allocID_valid, inspection_completed, ts_enable,

bap_valid_flag, reqmat_valid_flag, SBWalloc_bytes_int, available_bytes) is --process

begin


case current_state is
when IDLE =>

IF FCLK='1' then

next_state<=WAIT_SURPLUS_EN;

else


next_state <= IDLE;

end if;


when WAIT_SURPLUS_EN =>

if ts_enable = '1' then

next_state <= wait_sbwti_valid; --MEMORY_ACCESS;

else


next_state <= WAIT_SURPLUS_EN;

end if;


when wait_sbwti_valid =>

if fclk='1' then

next_state<=WAIT_SURPLUS_EN;

elsif allocID_valid = '1' then

next_state <= MEMORY_ACCESS;

elsif inspection_completed = '1' then

next_state<=idle;

else


next_state <= wait_sbwti_valid;

end if;


when MEMORY_ACCESS =>

if bap_valid_flag = '1' and reqmat_valid_flag = '1' then

next_state <= PRELIMINARY_CALCULATIONS;

else


next_state <= MEMORY_ACCESS;

end if;


when PRELIMINARY_CALCULATIONS=>

next_state <=PREPARE_SBWStruct;

when PREPARE_SBWStruct =>

next_state <= deliver_SBWstruct;

when DELIVER_SBWSTRUCT =>

if (not (SBWalloc_bytes_int

next_state <= WAIT_NEW_FRAME;

elsif inspection_completed = '1' then

next_state <= CLOSE_SBW;

else


next_state <= wait_sbwti_valid;

end if;
when CLOSE_SBW=>

next_state<=IDLE;

when WAIT_NEW_FRAME =>

if ts_enable='1' then

next_state<=DELIVER_SBWSTRUCT;

else

next_state<=WAIT_NEW_FRAME;



end if;

when OTHERS =>

next_state <= IDLE;

end case;

end process;

output_proc:process(clk, rstn) is --process

begin

if rstn = '0' then



bap_param_reg <= (others => '0');

reqmat_param_reg <= (others => '0');

allocid_reg <= (others => '0');

bap_valid_flag <= '0';

reqmat_valid_flag <= '0';

SBWstruct_RDY <= '0';

update_reqmat_cmd <= '0';

SBWstruct_allocid <= (others => '0');

SBWonu_id(7 downto 0) <= (others => '0');

SBWalloc_bytes_int <= (others => '0');

SBWpcbu_fec(4) <='0';

SBWpcbu_fec(2 downto 0) <= (others => '0');

stall_inspection <= '0';

NSR <= '0';

FEC_enabled <= '0';

PBrep <= '0';

mem_addr <= (others => '0');

mem_req <= '0';

allocation_bytes <= (others =>'0');

t_cont <= "01";

available_bytes_int<= (others =>'0');
elsif rising_edge(clk) then

if available_bytes>fixed_difference then

available_bytes_int(14 downto 0)<=available_bytes-fixed_difference;

else


available_bytes_int(14 downto 0)<= (others =>'0');

end if;


SBWstruct_RDY <= '0';

update_reqmat_cmd <= '0';

SBWstruct_allocid <= (others => '0');

mem_addr <= (others => '0');

mem_req <= '0';

case current_state is


when wait_sbwti_valid =>

if allocID_valid = '1' then

allocID_reg <= allocid;

mem_addr <= allocid;

mem_req <= allocID_valid;

end if;


when MEMORY_ACCESS =>

if bap_valid = '1' then

bap_valid_flag <= '1';

bap_param_reg <= bap_param(47 downto 40) & bap_param(37 downto 33) & bap_param(31 downto 16); --maxTB

PBrep <= bap_param(47);

NSR <= bap_param(39);

SBWpcbu_fec(4) <= bap_param(39);

t_cont <= bap_param(37 downto 36);

FEC_enabled <= bap_param(33);

end if;
if reqmat_valid = '1' then

reqmat_valid_flag <= '1';

reqmat_param_reg <= reqmat_param;

end if;

when PRELIMINARY_CALCULATIONS =>



reqmat_valid_flag <= '0';

bap_valid_flag <= '0';

if NSR='1' then

if (not (reqmat_param_reg(20 downto 16)= "00000")) or (bap_param_reg(15 downto 0) < reqmat_param_reg(15 downto 0)) then -- minTB_bytes < requested_bytes ###this option can be ORed with the IF###

SBWalloc_bytes_int <= bap_param_reg(15 downto 0);

else


if FEC_enabled ='0' then

SBWalloc_bytes_int<=NSR_fixed_allocation;

else

SBWalloc_bytes_int<=FEC_NSR_fixed_allocation;



end if;

end if;


else

if (not (reqmat_param_reg(20 downto 16)= "00000")) or bap_param_reg(15 downto 0) < reqmat_param_reg(15 downto 0) then -- minTB_bytes < requested_bytes ###this option can be ORed with the IF###

SBWalloc_bytes_int <= bap_param_reg(15 downto 0);

else


if PBrep ='1' then --- DBRu ='1' then

if reqmat_param_reg(15 downto 0)>0 then

if FEC_enabled='1' and reqmat_param_reg(15 downto 0)<16 then

sbwalloc_bytes_int<= reqmat_param_reg(15 downto 0)+DBRu_length+16;

else

sbwalloc_bytes_int<= reqmat_param_reg(15 downto 0)+DBRu_length;



end if;

else


if FEC_enabled='0' then

SBWalloc_bytes_int<=DBRu_length;

else

SBWalloc_bytes_int<=DBRu_length+16;



end if;

end if;


else

SBWalloc_bytes_int<= reqmat_param_reg(15 downto 0);

end if; -- DBRu

end if; -- relation between Min TB and request

end if; -- NSR

when PREPARE_SBWStruct=>

if SBWalloc_bytes_int>available_bytes_int then

SBWAlloc_bytes_int<=available_bytes_int;

end if;

when DELIVER_SBWSTRUCT =>



SBWstruct_allocid <= allocID_reg;

SBWonu_id (6 downto 0) <= bap_param_reg(27 downto 21);

SBWpcbu_fec(0) <= bap_param_reg(16);

if PBrep='1' then

SBWpcbu_fec(2 downto 1)<=bap_param_reg(18 downto 17);

else


SBWpcbu_fec(2 downto 1)<="00";

end if;
if SBWalloc_bytes_int < available_bytes then --- it was < available_bytes_int --########### offset to be added

if sbwalloc_bytes_int /="0000000000000000" then

SBWstruct_RDY <= '1';

else

SBWstruct_RDY <= '0';



end if;

else


SBWstruct_RDY <= '0';

end if;
if ((SBWalloc_bytes_int < available_bytes) and NSR='0' and (not (bap_param_reg(20 downto 19)="01")) AND reqmat_param_reg /= "000000000000000000000") then

update_reqmat_cmd<='1';

else


update_reqmat_cmd<='0';

end if;


when CLOSE_SBW =>

when OTHERS =>

null;

end case;



if (current_state = wait_sbwti_valid OR current_state = DELIVER_SBWSTRUCT) and (not (available_bytes_int

stall_inspection <= '0';

else

stall_inspection <= '1';



end if;

if current_state=DELIVER_SBWSTRUCT then

if PBrep ='1' then

allocation_bytes <= SBWalloc_bytes_int-2;

else

allocation_bytes <= SBWalloc_bytes_int;



end if;

end if;


end if;
end process output_proc;

--------------------------------------------------------

end architecture sbw_ts_a;

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 26/10/03

-------------------------------------------

-- Design Unit Name : sbw_tu

-- Purpose : The update of all the active and non-zero minSDI timers.

--

-- File Name : sbw_tu.vhd



-------------------------------------------

-- Assumptions ----------------------------

-------------------------------------------

--

-- 1. The current entity is triggered by the FCLK.



-- 2. It needs 3 clock periods for every active AllocId and 2 for every non active, hence it keeps

-- mema_en high for 2048+#active allocId clock periods. At the end, memx_scan_fin is asserted enabling the access to the min SDI

-- timer memory by other entities (sbw_ti).

-------------------------------------------

-------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;
entity sbw_tu is

generic(


allocid_gen : positive := 10;

sdi_mem_gen : positive := 15

);

port(


rstn : in std_logic;

clk : in std_logic;

fclk : in std_logic;

--minsdi i/f a

mema_addr : out std_logic_vector(allocid_gen - 1 downto 0);

-- mema_nd : out std_logic;

mema_en : out std_logic;

mema_we : out std_logic;

mema_din : in std_logic_vector(sdi_mem_gen - 1 downto 0); --input from memory

mema_dout : out std_logic_vector(sdi_mem_gen - 1 downto 0) ; --output to memory

memx_scan_fin : out std_logic

);

end entity sbw_tu;


----------------------------------------------------------------------
architecture sbw_tu_a of sbw_tu is
type TStates is (IDLE,

FETCH_FROM_MEMORY,

WAIT_MEM_RESPONSE1,

WAIT_MEM_RESPONSE2,

SEND_TO_MEM);

signal current_state, next_state : TStates;

signal memx_addr : std_logic_vector(allocid_gen - 1 downto 0);

begin
----------------------------------------------------------------------

mema_addr <= memx_addr;

----------------------------------------------------------------------


----------------------------------------------------------------------

------------ Finite State Machine ------------------------------------

----------------------------------------------------------------------

process(clk, rstn) is

begin
if rstn = '0' then

current_state <= IDLE;

elsif rising_edge(clk) then

current_state <= next_state;

end if;
end process;
sbw_tu_fsm_comb: process(fclk, mema_din, memx_addr, current_state) is

begin
case current_state is


when IDLE =>

if fclk = '1' then

next_state <= FETCH_FROM_MEMORY;

else


next_state <= IDLE;

end if;


when FETCH_FROM_MEMORY =>

next_state <= WAIT_MEM_RESPONSE1;

when WAIT_MEM_RESPONSE1=>

next_state <= WAIT_MEM_RESPONSE2;

when WAIT_MEM_RESPONSE2 =>

if mema_din(14 downto 13) = "11" then

next_state <= SEND_TO_MEM;

else


if memx_addr = "1111111111" then

next_state <= IDLE;

else

next_state <= WAIT_MEM_RESPONSE1; --FETCH_FROM_MEMORY;



end if;

end if;


when SEND_TO_MEM =>

if memx_addr = "1111111111" then

next_state <= IDLE;

else


next_state <= WAIT_MEM_RESPONSE1; --FETCH_FROM_MEMORY;

end if;


when others =>

next_state <= IDLE;

end case;
end process;
----------------------------------------------------------------------

------------ OUTPUTS ------------------------------------------------

----------------------------------------------------------------------

process(clk, rstn) is

begin
if rstn = '0' then

mema_we <= '0';

mema_en <= '0';

memx_addr <= (others => '0');

memx_scan_fin <= '0';

mema_dout <= (others => '0');

elsif rising_edge(clk) then

case current_state is

when IDLE =>

if fclk = '1' then

mema_en <= '1';

mema_we <= '0';

memx_addr <= "0000000000";

else


mema_en <= '0';

end if;


when FETCH_FROM_MEMORY =>

mema_en <= '1';

mema_we <= '0';

when WAIT_MEM_RESPONSE1 =>

when WAIT_MEM_RESPONSE2 =>

if mema_din(14 downto 13) /= "11" then

memx_addr <=memx_addr +1;

else


mema_we <= '1';

if mema_din(12 downto 0) = "0000000000000" then

mema_dout <= mema_din(14 downto 13) & "0000000000000";

else


mema_dout <= mema_din(14 downto 13) & (mema_din(12 downto 0) - 1);

end if;


end if;

when send_to_mem =>

mema_we <= '0';

memx_addr <=memx_addr +1;

when others =>

null;


end case;

if current_state=wait_mem_response2 and memx_addr="1111111111" then

memx_scan_fin<='1';

else


memx_scan_fin<='0';

end if;


end if;

end process;


end architecture sbw_tu_a;

------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--


-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"

-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--


-- Xilinx products are not intended for use in life support

-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--


-- (c) Copyright 1995-2003 Xilinx, Inc.

-- All rights reserved.

--------------------------------------------------------------------------------

-- You must compile the wrapper file sdi_mem.vhd when simulating

-- the core, sdi_mem. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Guide".
-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY sdi_mem IS

port (

addra: IN std_logic_VECTOR(9 downto 0);



addrb: IN std_logic_VECTOR(9 downto 0);

clka: IN std_logic;

clkb: IN std_logic;

dina: IN std_logic_VECTOR(14 downto 0);

dinb: IN std_logic_VECTOR(14 downto 0);

douta: OUT std_logic_VECTOR(14 downto 0);

doutb: OUT std_logic_VECTOR(14 downto 0);

ena: IN std_logic;

enb: IN std_logic;

wea: IN std_logic;

web: IN std_logic);

END sdi_mem;


ARCHITECTURE sdi_mem_a OF sdi_mem IS
component wrapped_sdi_mem

port (


addra: IN std_logic_VECTOR(9 downto 0);

addrb: IN std_logic_VECTOR(9 downto 0);

clka: IN std_logic;

clkb: IN std_logic;

dina: IN std_logic_VECTOR(14 downto 0);

dinb: IN std_logic_VECTOR(14 downto 0);

douta: OUT std_logic_VECTOR(14 downto 0);

doutb: OUT std_logic_VECTOR(14 downto 0);

ena: IN std_logic;

enb: IN std_logic;

wea: IN std_logic;

web: IN std_logic);

end component;
-- Configuration specification

for all : wrapped_sdi_mem use entity XilinxCoreLib.blkmemdp_v5_0(behavioral)


generic map(

c_reg_inputsb => 0,

c_reg_inputsa => 0,

c_has_ndb => 0,

c_has_nda => 0,

c_ytop_addr => "1024",

c_has_rfdb => 0,

c_has_rfda => 0,

c_yena_is_high => 1,

c_ywea_is_high => 1,

c_yclka_is_rising => 1,

c_yhierarchy => "hierarchy1",

c_ysinita_is_high => 1,

c_ybottom_addr => "0",

c_width_b => 15,

c_width_a => 15,

c_sinita_value => "0",

c_sinitb_value => "0",

c_limit_data_pitch => 18,

c_write_modeb => 0,

c_write_modea => 0,

c_has_rdyb => 0,

c_has_rdya => 0,

c_yuse_single_primitive => 0,

c_addra_width => 10,

c_addrb_width => 10,

c_has_limit_data_pitch => 0,

c_default_data => "0",

c_pipe_stages_b => 0,

c_yweb_is_high => 1,

c_yenb_is_high => 1,

c_pipe_stages_a => 0,

c_yclkb_is_rising => 1,

c_enable_rlocs => 0,

c_ysinitb_is_high => 1,

c_has_web => 1,

c_has_default_data => 1,

c_has_sinitb => 0,

c_has_wea => 1,

c_has_sinita => 0,

c_has_dinb => 1,

c_has_dina => 1,

c_ymake_bmm => 0,

c_has_enb => 1,

c_has_ena => 1,

c_depth_b => 1024,

c_mem_init_file => "mif_file_16_1",

c_depth_a => 1024,

c_has_doutb => 1,

c_has_douta => 1,

c_yprimitive_type => "16kx1");

BEGIN
U0 : wrapped_sdi_mem

port map (

addra => addra,

addrb => addrb,

clka => clka,

clkb => clkb,

dina => dina,

dinb => dinb,

douta => douta,

doutb => doutb,

ena => ena,

enb => enb,

wea => wea,

web => web);

END sdi_mem_a;


-- synopsys translate_on

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 12/9/03

-------------------------------------------

-- Design Unit Name : Update ReqMat

-- Purpose : Updates the Request Matrix after request of the gbw_ts or the sbw_ts.

-- File Name : update_reqmat.vhd

---------------------------------------------

-- Description ----------------------------

-- 1. It receives as input from gbwts or sbwts the allocID, valid, gbw_allocation_bytes_bytes

-- req_data_in (the request number) and the tcont. Hence its responsibility is to write

-- in the request matrix the value req_data_in - allocation bytes. In case that the Tcont is 3 or 4

-- and the req_data_in equals the allocation bytes, the respective flag is reset.

-----------------------------------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;


entity update_reqmat is

port (


clk :in std_logic;

rstn : in std_logic;

--gbwts i/f

gbw_valid : in std_logic;

gbw_allocID : in std_logic_vector (9 downto 0);

gbw_allocation_bytes : in std_logic_vector (15 downto 0);

gbw_req_data_in : in std_logic_vector(20 downto 0);

gbw_tcont : in std_logic_vector (2 downto 0); --3bits tcont_type

--sbwts i/f

sbw_valid : in std_logic;

sbw_allocID : in std_logic_vector (9 downto 0);

sbw_allocation_bytes : in std_logic_vector (15 downto 0);

sbw_req_data_in : in std_logic_vector(20 downto 0);

sbw_tcont : in std_logic_vector (2 downto 0); --3bits tcont_type

-- Signals for Request Matrix ------------------

req_cs : out std_logic;

req_we : out std_logic;

req_ack : in std_logic;

req_addr : out std_logic_vector(9 downto 0); --Idio me tou AllocID

req_data_out : out std_logic_vector(20 downto 0);

---- dba_rx i/f

dbarx_flag_selection : in std_logic;

dbarx_flag_addr : in std_logic_vector(5 downto 0);

--tcont3/tcont4 regions i/f

flag_cs : out std_logic;

flag_we : out std_logic;

flag_ack : in std_logic;

flag_selection : out std_logic;

flag_addr : out std_logic_vector(5 downto 0);

flag_data_out : out std_logic_vector (15 downto 0);

flag3_data_in : in std_logic_vector (15 downto 0);

flag4_data_in : in std_logic_vector (15 downto 0)

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