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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--


-- Xilinx products are not intended for use in life support

-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--


-- (c) Copyright 1995-2002 Xilinx, Inc.

-- All rights reserved.

--------------------------------------------------------------------------------

-- You must compile the wrapper file bap_mem.vhd when simulating

-- the core, bap_mem. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "Coregen Users Guide".
-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Express, Exemplar and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY bap_mem IS

port (

addr: IN std_logic_VECTOR(9 downto 0);



clk: IN std_logic;

din: IN std_logic_VECTOR(47 downto 0);

dout: OUT std_logic_VECTOR(47 downto 0);

en: IN std_logic;

nd: IN std_logic;

rfd: OUT std_logic;

rdy: OUT std_logic;

we: IN std_logic);

END bap_mem;
ARCHITECTURE bap_mem_a OF bap_mem IS
component wrapped_bap_mem

port (


addr: IN std_logic_VECTOR(9 downto 0);

clk: IN std_logic;

din: IN std_logic_VECTOR(47 downto 0);

dout: OUT std_logic_VECTOR(47 downto 0);

en: IN std_logic;

nd: IN std_logic;

rfd: OUT std_logic;

rdy: OUT std_logic;

we: IN std_logic);

end component;


-- Configuration specification

for all : wrapped_bap_mem use entity XilinxCoreLib.blkmemsp_v4_0(behavioral)

generic map(

c_sinit_value => "0",

c_reg_inputs => 0,

c_yclk_is_rising => 1,

c_has_en => 1,

c_ysinit_is_high => 1,

c_ywe_is_high => 1,

c_ytop_addr => "1024",

c_yprimitive_type => "16kx1",

c_yhierarchy => "hierarchy1",

c_has_rdy => 1,

c_has_limit_data_pitch => 0,

c_write_mode => 0,

c_width => 48,

c_yuse_single_primitive => 0,

c_has_nd => 1,

c_enable_rlocs => 0,

c_has_we => 1,

c_has_rfd => 1,

c_has_din => 1,

c_ybottom_addr => "0",

c_pipe_stages => 0,

c_yen_is_high => 1,

c_depth => 1024,

c_has_default_data => 1,

c_limit_data_pitch => 18,

c_has_sinit => 0,

c_mem_init_file => "mif_file_16_1",

c_default_data => "0",

c_ymake_bmm => 0,

c_addr_width => 10);

BEGIN
U0 : wrapped_bap_mem

port map (

addr => addr,

clk => clk,

din => din,

dout => dout,

en => en,

nd => nd,

rfd => rfd,

rdy => rdy,

we => we);

END bap_mem_a;
-- synopsys translate_on

------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--


-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"

-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--


-- Xilinx products are not intended for use in life support

-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--


-- (c) Copyright 1995-2002 Xilinx, Inc.

-- All rights reserved.

--------------------------------------------------------------------------------

-- You must compile the wrapper file reqmat_mem.vhd when simulating

-- the core, reqmat_mem. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "Coregen Users Guide".
-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Express, Exemplar and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY reqmat_mem IS

port (

addr: IN std_logic_VECTOR(9 downto 0);



clk: IN std_logic;

din: IN std_logic_VECTOR(20 downto 0);

dout: OUT std_logic_VECTOR(20 downto 0);

en: IN std_logic;

nd: IN std_logic;

rfd: OUT std_logic;

rdy: OUT std_logic;

we: IN std_logic);

END reqmat_mem;
ARCHITECTURE reqmat_mem_a OF reqmat_mem IS
component wrapped_reqmat_mem

port (


addr: IN std_logic_VECTOR(9 downto 0);

clk: IN std_logic;

din: IN std_logic_VECTOR(20 downto 0);

dout: OUT std_logic_VECTOR(20 downto 0);

en: IN std_logic;

nd: IN std_logic;

rfd: OUT std_logic;

rdy: OUT std_logic;

we: IN std_logic);

end component;


-- Configuration specification

for all : wrapped_reqmat_mem use entity XilinxCoreLib.blkmemsp_v4_0(behavioral)

generic map(

c_sinit_value => "0",

c_reg_inputs => 0,

c_yclk_is_rising => 1,

c_has_en => 1,

c_ysinit_is_high => 1,

c_ywe_is_high => 1,

c_ytop_addr => "1024",

c_yprimitive_type => "16kx1",

c_yhierarchy => "hierarchy1",

c_has_rdy => 1,

c_has_limit_data_pitch => 0,

c_write_mode => 0,

c_width => 21,

c_yuse_single_primitive => 0,

c_has_nd => 1,

c_enable_rlocs => 0,

c_has_we => 1,

c_has_rfd => 1,

c_has_din => 1,

c_ybottom_addr => "0",

c_pipe_stages => 0,

c_yen_is_high => 1,

c_depth => 1024,

c_has_default_data => 1,

c_limit_data_pitch => 18,

c_has_sinit => 0,

c_mem_init_file => "mif_file_16_1",

c_default_data => "0",

c_ymake_bmm => 0,

c_addr_width => 10);

BEGIN
U0 : wrapped_reqmat_mem

port map (

addr => addr,

clk => clk,

din => din,

dout => dout,

en => en,

nd => nd,

rfd => rfd,

rdy => rdy,

we => we);

END reqmat_mem_a;
-- synopsys translate_on

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-- Date Start: 11/6/03

-------------------------------------------

-- Design Unit Name : DBA Report Receiver

-- Purpose : This entity uses the DBA reports received from the GLTP2

-- to update the pending request information

--

-- File Name : dba_report_rx.vhd



-------------------------------------------

-------------------------------------------

-- Description

-- The received DBA reports are stored in a FIFO, to guarantee that no report

-- will be lost due to a delay in a memory access.

-- Each time that a report along with the AllocID is read from the FIFO, the DBA_rx

-- reads the bap to check the T-CONT type of the AllocID. In case that this is of T-CONT 3 or 4

-- type the relevant flag is asserted. The report value is decoded based on the non-linear code

-- defined in the TC_standard, the decoded value is multiplied by 48 and stored in the request

-- memory, independent of the T-CONT type of the ALlocID.

--

-------------------------------------------



-----------------------------------------------------------------------------

-----------------------------------------------------------------------------

-- Note: when a report for an non FEC-enabled ONU arrives, the decoded report value is multiplied by 48

-- when a report for an FEC_enabled ONU arrives, the decoded report is multipled by 52 and 16 extra bytes are added.

-- this is because: the reporte queue length needs R'=(r*48)x16/239 + rx48 +16 bytes to travle in the upsrean

-- i.e.R'= rx51.4+16

-----------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity dba_rx is

port (

clk : in std_logic;



rstn : in std_logic;

--GXTP i/f

-- gxtp_clk : in std_logic;

dba_valid : in std_logic;

dba_bus : in std_logic_vector(11 downto 0);

--bap i/f

bap_cs : out std_logic;

bap_we : out std_logic; --Otan 1 tote Write, otan 0 tote read

bap_ack : in std_logic; --From Arbiter of Bap

bap_addr : out std_logic_vector(9 downto 0);

bap_data : in std_logic_vector(47 downto 0); -- the T-CONT type field

--reqmat i/f

reqmat_req : out std_logic;

reqmat_we : out std_logic;

reqmat_ack : in std_logic;

reqmat_addr : out std_logic_vector(9 downto 0); --Idio me tou AllocID

reqmat_data : out std_logic_vector(20 downto 0); -- Nonlinear coding is used.

-- update_reqmat i/f ---------

update_reqmat_addr : in std_logic_vector(5 downto 0);

update_reqmat_selection : in std_logic;

--tcont3/tcont4 regions i/f

flag_cs : out std_logic;

flag_we : out std_logic;

flag_ack : in std_logic;

flag_selection : out std_logic;

flag_addr : out std_logic_vector(5 downto 0);

--The MSB bit of the flag_addr signal is : 0 gia T-cont3

-- and 1 gia T-cont4

flag_data_out : out std_logic_vector (15 downto 0);

flag_data_in : in std_logic_vector (15 downto 0);

--afifo_dba i/f

fifo_dout : out std_logic_vector(19 downto 0);

fifo_din : in std_logic_vector(19 downto 0);

fifo_empty : in std_logic;

fifo_wr_en : out std_logic;

fifo_rd_en : out std_logic;

fifo_rd_ack :in std_logic

);

end entity dba_rx;



--------------------------------------------
architecture dba_rx_a of dba_rx is

---------------------------

type SStates is (WAIT_FOR_ALLOC_ID, WAIT_FOR_DBA_REPORT); --Input to fifo

type FStates is (READ_FROM_FIFO, WAIT_FIFO_RD_ACK, WAIT_FEC_ACK, PREPARE_REQUEST_VALUE, WRITE_REQMAT, WAIT_FOR_REQMAT_ACK); -- Fifo to reqmat

type BStates is (READ_FROM_FIFO, WAIT_FOR_BAP_ACK, TC_READ, wait_update_reqmat, TC_WRITE, WAIT_FOR_TC_ACK);--Fifo to Bap...tc stands for tcont

signal current_state: SStates;

signal reqmat_current_state: FStates;

signal bap_current_state: BStates;

signal fifo_data : std_logic_vector(3 downto 0);

signal fec_enabled : std_logic;

signal flag_addr_i : std_logic_vector (6 downto 0);

signal flag_data_i : std_logic_vector (15 downto 0);

signal reqmat_data_i : std_logic_vector (14 downto 0);

signal reqmat_data_temp : std_logic_vector (20 downto 0);

signal requests : std_logic_vector (7 downto 0);

signal dba_valid_sync : std_logic;

signal dba_bus_sync : std_logic_vector (11 downto 0);

---------------------------------------------------------------

begin

------------------------Unconditional Assignments--------------



---------------------------------------------------------------

flag_selection <= flag_addr_i(6);

flag_data_out <= flag_data_i;

bap_we <= '0'; --read

----------------------------------------------

-- Reads input and writes it to the FIFO ---

--------------------------------------------

input_to_fifo: process (rstn,clk) is

begin
if (rstn = '0') then

current_state <= WAIT_FOR_ALLOC_ID;

fifo_wr_en <= '0';

fifo_dout <= (others => '0');

elsif rising_edge(clk) then
case current_state is

when WAIT_FOR_ALLOC_ID =>

fifo_wr_en <= '0';

if dba_valid_sync = '1' then

current_state <= WAIT_FOR_DBA_REPORT;

else


current_state <= WAIT_FOR_ALLOC_ID;

end if;


fifo_dout (19 downto 8) <= dba_bus_sync (11 downto 0);

when WAIT_FOR_DBA_REPORT =>

fifo_dout (7 downto 0) <= dba_bus_sync (7 downto 0);

fifo_wr_en <= '1';

current_state <= WAIT_FOR_ALLOC_ID;

end case;


end if;
end process;

------------------------------------------------------------------------------

------------------- Reads from FIFO and updates the request matrix -----------

------------------------------------------------------------------------------

fifo_to_logic: process (rstn, clk)

begin
if rstn = '0' then

reqmat_current_state <= READ_FROM_FIFO;

fifo_rd_en <= '0';

fifo_data <= (others => '0');

reqmat_req <= '0';

reqmat_we <= '0';

reqmat_addr <= (others => '0');

reqmat_data <= (others => '0');

reqmat_data_i <= (others => '0');

reqmat_data_temp <= (others => '0');

elsif rising_edge(clk) then

if (reqmat_current_state = READ_FROM_FIFO) and (bap_current_state = READ_FROM_FIFO) then --****** Added 18/9/03

if fifo_empty = '0' then

fifo_rd_en <= '1';

reqmat_current_state <= WAIT_FIFO_RD_ACK;

end if;

end if;


if reqmat_current_state=WAIT_FIFO_RD_ACK then

fifo_rd_en <= '0';


if fifo_rd_ack='1' then

reqmat_current_state <= WAIT_FEC_ACK; --wait_for_reqmat_ack;

fifo_data <= fifo_din(11 downto 8);

else


reqmat_current_state <= WAIT_FIFO_RD_ACK;

end if;
end if;

if reqmat_current_state=WAIT_FIFO_RD_ACK and fifo_rd_ack='1' then

reqmat_addr <= fifo_din(17 downto 8) ;

------------------NON LINEAR CODING USED

if fifo_din(7) = '0' then

reqmat_data_i(14 downto 7) <= "00000000";

reqmat_data_i(6 downto 0) <= fifo_din(6 downto 0);

elsif fifo_din(7 downto 6) = "10" then

reqmat_data_i(14 downto 7) <= "00000001";

reqmat_data_i(6 downto 1) <= fifo_din(5 downto 0);

reqmat_data_i(0) <= '1';

elsif fifo_din(7 downto 5) = "110" then

reqmat_data_i(14 downto 8) <= "0000001";

reqmat_data_i(7 downto 3) <= fifo_din(4 downto 0);

reqmat_data_i(2 downto 0) <= "111";

elsif fifo_din(7 downto 4) = "1110" then

reqmat_data_i(14 downto 9) <= "000001";

reqmat_data_i(8 downto 5) <= fifo_din(3 downto 0);

reqmat_data_i(4 downto 0) <= "11111";

elsif fifo_din(7 downto 3) = "11110" then

reqmat_data_i(14 downto 10) <= "00001";

reqmat_data_i(9 downto 7) <= fifo_din(2 downto 0);

reqmat_data_i(6 downto 0) <= "1111111";

elsif fifo_din(7 downto 2) = "111110" then

reqmat_data_i(14 downto 11) <= "0001";

reqmat_data_i(10 downto 9) <= fifo_din(1 downto 0);

reqmat_data_i(8 downto 0) <= "111111111";

elsif fifo_din(7 downto 1) = "1111110" then

reqmat_data_i(14 downto 12) <= "001";

reqmat_data_i(11) <= fifo_din(0);

reqmat_data_i(10 downto 0) <= "11111111111";

elsif fifo_din(7 downto 0) = "11111110" then

reqmat_data_i <= "011111111111111";

else

reqmat_data_i <= "011111111111111";



end if;

---------------------------------------------------------------------------

end if;

if reqmat_current_state=WAIT_FEC_ACK then

if bap_ack='1' then

reqmat_current_state<=PREPARE_REQUEST_VALUE;

else

reqmat_current_state<=WAIT_FEC_ACK;



end if;

end if;


if reqmat_current_state=PREPARE_REQUEST_VALUE then

reqmat_current_state <= WRITE_REQMAT;

reqmat_data_temp<=('0' & reqmat_data_i & "00000")+ ("00" & reqmat_data_i & "0000");

end if;


if reqmat_current_state=WRITE_REQMAT then

reqmat_current_state <= WAIT_FOR_REQMAT_ACK;

reqmat_req <= '1';

reqmat_we <= '1';


if fec_enabled='0' then

reqmat_data<=reqmat_data_temp;

else

if reqmat_data_temp="000000000000000000000" then



reqmat_data<=(others =>'0');

else


reqmat_data<=reqmat_data_temp+("0000" & reqmat_data_i & "00")+ "00000000000000010000";

end if;


end if;
end if;

if reqmat_current_state = WAIT_FOR_REQMAT_ACK then

reqmat_req <= '0';

reqmat_we <= '0';

if reqmat_ack = '1' then

reqmat_current_state <= READ_FROM_FIFO;

end if;
end if;
end if;
end process;

--------------------------------------------

-- Main Logic ------------------------------

--------------------------------------------

logic :process (rstn,clk)

begin
if rstn = '0' then

bap_cs <= '0';

bap_addr <= (others => '0');

bap_current_state <= READ_FROM_FIFO;

flag_cs <= '0';

flag_we <= '0';

flag_addr <=(others =>'0');

flag_addr_i <= (others => '0');

flag_data_i <= (others => '0');

fec_enabled <= '0';

requests <= (others => '0');

elsif rising_edge(clk) then

case bap_current_state is

when READ_FROM_FIFO =>

if (reqmat_current_state=WAIT_FIFO_RD_ACK) and (fifo_rd_ack='1') then

bap_cs <= '1';

bap_addr <= fifo_din(17 downto 8);

bap_current_state <= WAIT_FOR_BAP_ACK;

requests <= fifo_din(7 downto 0) ;

flag_addr_i(5 downto 0) <= fifo_din(17 downto 12);

end if;


when WAIT_FOR_BAP_ACK =>

bap_cs <='0';

if bap_ack = '1' then

flag_we <= '0'; --read;

fec_enabled <=bap_data(33);

if bap_data(37 downto 36) = "11" then -- check whether "11" is T-CONT 3

if bap_data(32) = '1' then --if this allocID is active

flag_addr_i(6) <= '0'; -- TC3

if update_reqmat_addr="000000" and update_reqmat_selection = '0' then

bap_current_state <=TC_READ;

flag_cs <= '1';

flag_addr<= flag_addr_i(5 downto 0);

else

bap_current_state <=wait_update_reqmat;



end if;

else


bap_current_state <=READ_FROM_FIFO;

end if;


elsif bap_data(37 downto 36) = "00" then -- check whether "00" is T-CONT 4

if bap_data(32) = '1' then --if this allocID is activated

flag_addr_i(6) <= '1'; -- TC4

if update_reqmat_addr="000000" and update_reqmat_selection = '1' then

bap_current_state <=TC_READ;

flag_cs <= '1';

flag_addr<= flag_addr_i(5 downto 0);

else


bap_current_state <=wait_update_reqmat;

end if;


else

bap_current_state <=READ_FROM_FIFO;

end if;

else


flag_cs <= '0';

flag_addr_i(6) <= '0';

bap_current_state <= READ_FROM_FIFO ;

end if;


end if; -- end of bap ack

when wait_update_reqmat =>

if update_reqmat_addr="000000" then

bap_current_state <=TC_READ;

flag_cs <= '1';

flag_addr<= flag_addr_i(5 downto 0);

else

bap_current_state <=wait_update_reqmat;



end if;

when TC_READ =>

flag_cs <= '0';

if flag_ack = '1' then

flag_data_i <= flag_data_in;

bap_current_state <= TC_WRITE;

end if;

when TC_WRITE =>



flag_cs <= '1';

flag_we <= '1';

if requests="00000000" then

flag_data_i(conv_integer(fifo_data)) <= '0';

else

flag_data_i(conv_integer(fifo_data)) <= '1';



end if;

bap_current_state <= WAIT_FOR_TC_ACK;

when WAIT_FOR_TC_ACK =>

flag_we <= '0';

flag_cs <= '0';

flag_addr<=(others =>'0');

if flag_ack = '1' then

bap_current_state <= READ_FROM_FIFO;

end if;

end case;



end if;

end process;

input_o_fifo: process (rstn,clk) is

begin


if (rstn = '0') then

dba_valid_sync<= '0';

dba_bus_sync <= (others =>'0');

elsif rising_edge(clk) then

dba_valid_sync<=dba_valid;

dba_bus_sync <=dba_bus;

end if;

end process;


end architecture dba_rx_a;

------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--


-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"

-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--


-- Xilinx products are not intended for use in life support

-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--


-- (c) Copyright 1995-2002 Xilinx, Inc.

-- All rights reserved.

--------------------------------------------------------------------------------

-- You must compile the wrapper file afifo_dba.vhd when simulating

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