Σχεδιασμός και Υλοποίηση Πρωτοκόλλου mac για Παθητικά Οπτικά Δίκτυα gpon




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bap_addr <= allocID(9 downto 0);


------ frame clock process generator ---------------------------------

fclk_proc: process(rstn, clk) is


begin

if rstn = '0' then

cnt <= 1;

frame_number_s <= 0;

fclk_int <= '0';
elsif rising_edge(clk) then

if fclk_int = '1' then

frame_number_s <= frame_number_s + 1;

end if;


if cnt < conv_integer(frame_duration) then
cnt <= cnt + 1;

else


cnt <= 1;

end if;


if cnt = 1 then

fclk_int <= '1';

else

fclk_int <= '0';



end if;

end if;
end process;

--------Write to minsdi parameters memory -----------------------------------

process(clk, rstn) is

begin
if rstn = '0' then

sbw_memb_enb <= '0';

sbw_memb_dinb <= (others => '0');

sbw_memb_web <= '0';

wait_access_op<='0';

elsif rising_edge(clk) then


if allocID_valid = '1' then -- resonu(3) & '1' & minsdi;

sbw_memb_dinb <= activate & activate & minsdi;

if ((ResONU(6 downto 4) = TCONT3_con OR ResONU(6 downto 4) = TCONT4_con) and activate='1') or activate='0' then -- TCONT3 and TCONT4

if sbwti_addr="0000000000" then

sbw_memb_enb <= '1';

sbw_memb_web <= '1';

wait_access_op<='0';

else


wait_access_op<='1';

sbw_memb_enb <= '0';

sbw_memb_web <= '0';

end if;


end if;

else -- sbw_ti is accessing the minsdi parameters memory

if wait_access_op='1' then

if sbwti_addr="0000000000" then

sbw_memb_enb <= '1';

sbw_memb_web <= '1';

wait_access_op<='0';

else


wait_access_op<='1';

sbw_memb_enb <= '0';

sbw_memb_web <= '0';

end if;


else

sbw_memb_enb <= '0';

sbw_memb_web <= '0';

end if;


end if;

end if;


end process;
----------------------------------------------------------------------

bap_proc: process(clk, rstn)

begin
if rstn = '0' then

bap_en <= '0';

bap_we <= '0';

bap_douta <= (others => '0');

elsif rising_edge(clk) then

if allocid_valid = '1' and allocID(allocID_gen)='1' then

bap_en <= '1';

bap_we <= '1';

-----------DBA reporting+ resonu+ NSR+TCONT + PCBu + FEC enable+ actdeact

----------- + maxTB + minTB

bap_douta <= resonu(2) & resonu(14 downto 4) & resonu(1 downto 0) & resONU(3) & activate & maxTB & minTB;

else


bap_en <= '0';

bap_we <= '0';

end if;

end if;


end process;

----------------------------------------------------------------------


active_onus_proc : process(clk, rstn) is

begin
if rstn = '0' then


active_ONUs_ID <= (others => '0');

FEC_enabled_ONUs_int<= (others => '0');

elsif rising_edge(clk) then
if onu_valid = '1' then

active_ONUs_ID(conv_integer(ONU_info(6 downto 0))) <= ONU_info(8);

FEC_enabled_ONUs_int(conv_integer(ONU_info(6 downto 0))) <=ONU_info(9);

end if;


end if;
end process active_onus_proc;

end architecture mem_initializer_a;

------------------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--

-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"



-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--

-- Xilinx products are not intended for use in life support



-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--

-- (c) Copyright 1995-2003 Xilinx, Inc.



-- All rights reserved.

-------------------------------------------------------------------------------

-- You must compile the wrapper file max_sdi_mem.vhd when simulating

-- the core, max_sdi_mem. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Guide".


-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY max_sdi_mem IS

port (

addr: IN std_logic_VECTOR(9 downto 0);



clk: IN std_logic;

din: IN std_logic_VECTOR(14 downto 0);

dout: OUT std_logic_VECTOR(14 downto 0);

en: IN std_logic;

we: IN std_logic);

END max_sdi_mem;


ARCHITECTURE max_sdi_mem_a OF max_sdi_mem IS
component wrapped_max_sdi_mem

port (


addr: IN std_logic_VECTOR(9 downto 0);

clk: IN std_logic;

din: IN std_logic_VECTOR(14 downto 0);

dout: OUT std_logic_VECTOR(14 downto 0);

en: IN std_logic;

we: IN std_logic);

end component;
-- Configuration specification

for all : wrapped_max_sdi_mem use entity XilinxCoreLib.blkmemsp_v5_0(behavioral)


generic map(

c_sinit_value => "0",

c_reg_inputs => 0,

c_yclk_is_rising => 1,

c_has_en => 1,

c_ysinit_is_high => 1,

c_ywe_is_high => 1,

c_ytop_addr => "1024",

c_yprimitive_type => "16kx1",

c_yhierarchy => "hierarchy1",

c_has_rdy => 0,

c_has_limit_data_pitch => 0,

c_write_mode => 0,

c_width => 15,

c_yuse_single_primitive => 0,

c_has_nd => 0,

c_enable_rlocs => 0,

c_has_we => 1,

c_has_rfd => 0,

c_has_din => 1,

c_ybottom_addr => "0",

c_pipe_stages => 0,

c_yen_is_high => 1,

c_depth => 1024,

c_has_default_data => 1,

c_limit_data_pitch => 18,

c_has_sinit => 0,

c_mem_init_file => "mif_file_16_1",

c_default_data => "0",

c_ymake_bmm => 0,

c_addr_width => 10);

BEGIN
U0 : wrapped_max_sdi_mem

port map (

addr => addr,

clk => clk,

din => din,

dout => dout,

en => en,

we => we);

END max_sdi_mem_a;


-- synopsys translate_on

------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

-------------------------------------------

-- Design Unit Name : gbw_ti

-- Purpose : updates the maxSDI timers.

--

-- File Name : gbw_ti.vhd



-------------------------------------------

-------------------------------------------

-- Description

-----------------------------------------

-- This entity reads the maxSDI values memory and each time that an active

-- timer is detected (which is idnicated by the 2 MSBits), the timer is

-- decreased by one, unless it has reached zero value. In this case, the

-- respective AllocID is stored in a FIFO (to trigger the service of the

-- relevant AllocID) and the timer is set equal to the AllocID's Max SDI

-- parameter (stored in the MAX SDI parameter memory).

-- To avoid conflicts with mem initialiser in the MAX SDI parameters memory,

-- the gbw_ti takes the responsibility of writting the max SDI parameter and

-- max SDI values memory every time that a new AllocId is activated or

-- deactivated.

-------------------------------------------

-- Design note:

-- 1. The current entity is triggered by the signal FCLK that appears at its

-- port. This signal is connected to the gbw_assigned signal at the top

-- level to avoid using two fifos, as explained in the MAC controller specs

-- doc.


-- 2. It needs 4 clock periods for every active AllocId and 3 for every non

-- active, hence it keeps mema_en high for 3x1024+#activeAllocIds clock

-- periods.

--

-- Design improvement



-- 1. It can be designed in a pipelined way, to decrease the clock periods

-- spent to every AllocId by 1, as happens in sbw_tu entity.

-- 2. The arbitration of the MAX SDI parameters memory could be done using a

-- dedicated entity.

----------------------------------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;
entity gbw_ti is

generic(


allocid_gen : positive := 10;

SDI_gen : positive := 13;

sdi_mem_gen : positive := 15

);
port(

rstn : in std_logic;

clk : in std_logic;

fclk : in std_logic;

--- parallel bus ---------------------------------------------

AllocID_valid : in std_logic;

AllocId : in std_logic_vector (allocID_gen downto 0);

maxSDI : in std_logic_vector (SDI_gen - 1 downto 0);

--------------------------------------------------------------

--maxsdi i/f a

mema_addr : out std_logic_vector(allocid_gen - 1 downto 0);

mema_en : out std_logic;

mema_we : out std_logic;

mema_din : in std_logic_vector(sdi_mem_gen - 1 downto 0); --input

-- from memory 1

mema_dout : out std_logic_vector(sdi_mem_gen - 1 downto 0); --output

--to memory 1

--maxsdi i/f b

memb_addr : out std_logic_vector(allocid_gen - 1 downto 0);

memb_en : out std_logic;

memb_we : out std_logic;

memb_din : in std_logic_vector(sdi_mem_gen - 1 downto 0); --bit14 ,

--13 = activate

memb_dout : out std_logic_vector(sdi_mem_gen - 1 downto 0);

--bit12-0 = maxSDI value

--afifo i/f

fifo_dout : out std_logic_vector(allocid_gen - 1 downto 0);

fifo_we : out std_logic

);

end entity gbw_ti;



architecture gbw_ti_a of gbw_ti is
type TStates is (IDLE, FETCH_FROM_MEMORY, WAIT_MEM_RESPONSE,

SEND_TO_MEM, SEND_TO_FIFO, RELEASE, WRITE_NEW_ALLOCID);

signal current_state, next_state : TStates;

signal mema_reg : std_logic_vector(sdi_mem_gen - 1 downto 0);

signal memb_reg : std_logic_vector(sdi_mem_gen - 1 downto 0);

signal memx_addr,temp_addr : std_logic_vector(allocid_gen - 1 downto 0);

signal mema_new_alloc, memb_new_alloc : std_logic_vector(sdi_mem_gen - 1 downto 0);

signal AllocID_valid_int : std_logic;

signal activate : std_logic;

signal AllocID_int : std_logic_vector(allocid_gen - 1 downto 0);

signal allocID_written : std_logic;

begin
activate<=allocID(allocID_gen);

mema_addr <= memx_addr;

memb_addr <= memx_addr;


----------------------------------------------------------------------

------------ INITIALIZATION ------------------------------------------

----------------------------------------------------------------------

process(clk, rstn) is

begin
if rstn = '0' then

current_state <= IDLE;

elsif rising_edge(clk) then

current_state <= next_state;

end if;
end process;
----------------------------------------------------------------------

------------ Finite State Machine ------------------------------------

----------------------------------------------------------------------

process(fclk, mema_din, memb_din, memx_addr, allocid_valid_int, current_state) is

begin
case current_state is
when IDLE =>

if fclk = '1' then

next_state <= FETCH_FROM_MEMORY;

else


if allocid_valid_int='1' then

next_state<=write_new_allocid;

else

next_state <= IDLE;



end if;

end if;

when FETCH_FROM_MEMORY =>

next_state <= WAIT_MEM_RESPONSE;

when WAIT_MEM_RESPONSE =>

if mema_din = "110000000000001" and memb_din(13)='1' then

next_state <= SEND_TO_FIFO;

elsif mema_din(13) = '1' then

next_state <= SEND_TO_MEM;

else


next_state <= RELEASE;

end if;


when SEND_TO_MEM =>

next_state <= RELEASE;

when SEND_TO_FIFO =>

next_state <= RELEASE;

when RELEASE =>

if allocid_valid_int ='0' then

if memx_addr = "1111111111" then

next_state <= IDLE;

else

next_state <= FETCH_FROM_MEMORY;



end if;

else


next_state <= release; -- WRITE_NEW_ALLOCID;

END IF;


when WRITE_NEW_ALLOCID =>

next_state <= IDLE;

when others =>

next_state <= IDLE;

end case;
end process;
----------------------------------------------------------------------

------------ OUTPUTS ------------------------------------------------

----------------------------------------------------------------------

process(clk, rstn) is

begin
if rstn = '0' then

mema_we <= '0';

mema_en <= '0';

memb_we <= '0';

memb_en <= '0';

memx_addr <= (others => '0');

mema_dout <= (others => '0');

memb_dout <= (others => '0');

mema_reg <= (others => '0');

memb_reg <= (others => '0');

fifo_dout <= (others => '0');

fifo_we <= '0';

allocID_written<='0';

temp_addr<= (others => '0');


elsif rising_edge(clk) then
fifo_we <= '0';

allocID_written<='0';

case current_state is

when IDLE =>

if fclk = '1' then

mema_en <= '1';

mema_we <= '0';

memb_en <= '1';

memb_we <= '0';

memx_addr <= "0000000000";

else

if allocid_valid_int='1' then



mema_en <= '1';

mema_we <= '1';

memb_en <= '1';

memb_we <= '1';

mema_dout <=mema_new_alloc ;

memb_dout <=memb_new_alloc ;

memx_addr <=AllocID_int(9 downto 0);

else


mema_en <= '0';

memb_en <= '0';

end if;

end if;


when FETCH_FROM_MEMORY =>

mema_en <= '1';

memb_en <= '1';

mema_we <= '0';

when WAIT_MEM_RESPONSE =>

mema_en <= '1';

memb_en <= '1';

mema_reg <= mema_din;

memb_reg <= memb_din;

when SEND_TO_MEM =>

mema_en <= '1';

memb_en <= '1';

mema_we <= '1';

mema_dout <= mema_reg - 1;

when SEND_TO_FIFO =>

mema_en <= '1';

memb_en <= '1';

fifo_we <= '1';

fifo_dout <= memx_addr;

mema_we <= '1';

mema_dout <= memb_reg;

when RELEASE =>

mema_en <= '1';

memb_en <= '1';


fifo_we <= '0';

if allocID_valid_int='0' then

mema_we <= '0';

memb_we <= '0';

allocID_written<='0';

if allocID_written='0' then

if memx_addr = "1111111111" then

memx_addr <= (others => '0');

else

memx_addr <= memx_addr + 1;



end if;

ELSE


memx_addr<=temp_addr;

end if;


else

mema_we <= '1';

memb_we <= '1';

mema_dout <=mema_new_alloc ;

memb_dout <=memb_new_alloc ;

memx_addr<=AllocID_int(9 downto 0);

allocID_written<='1';

end if;


if allocID_written='0' then

if memx_addr = "1111111111" then

temp_addr <= (others => '0');

else


temp_addr <= memx_addr + 1;

end if;


end if;

when WRITE_NEW_ALLOCID =>

mema_en <= '1';

memb_en <= '1';

mema_we <= '0';

memb_we <= '0';

if memx_addr = "1111111111" then

memx_addr <= (others => '0');

else

memx_addr <= memx_addr + 1;



end if;

when others =>

null;

end case;



end if;

end process;


----------------------------------------------------------------------

write_new_alocID_proc: process(rstn, clk) is

begin

if rstn = '0' then



allocid_valid_int<='0';

mema_new_alloc <= (others =>'0');

memb_new_alloc <= (others =>'0');

AllocID_int <=(others =>'0');

elsif rising_edge(clk) then
if allocid_valid='1' then

allocid_valid_int<='1';

elsif ((current_state=release or next_state=write_new_allocid) and allocID_valid_int='1') then

allocid_valid_int<='0';

end if;

if allocID_valid = '1' then



mema_new_alloc <= activate & activate & maxsdi;

memb_new_alloc <= activate & activate & maxsdi;

AllocID_int <=AllocID(9 downto 0);

end if;


end if;
end process ;

----------------------------------------------------------------------


end architecture gbw_ti_a;

-------------------------------------------------------------------------------- This file is owned and controlled by Xilinx and must be used

-- solely for design, simulation, implementation and creation of

-- design files limited to Xilinx devices or technologies. Use

-- with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license.

--

-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"



-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-- FOR A PARTICULAR PURPOSE.

--

-- Xilinx products are not intended for use in life support



-- appliances, devices, or systems. Use in such applications are

-- expressly prohibited.

--

-- (c) Copyright 1995-2002 Xilinx, Inc.



-- All rights reserved.

--------------------------------------------------------------------------------

-- You must compile the wrapper file afifo_maxsdi.vhd when simulating

-- the core, afifo_maxsdi. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "Coregen Users Guide".


-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Express, Exemplar and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;

ENTITY afifo_maxsdi IS

port (

din : IN std_logic_VECTOR(9 downto 0);



wr_en : IN std_logic;

wr_clk : IN std_logic;

rd_en : IN std_logic;

rd_clk : IN std_logic;

ainit : IN std_logic;
dout : OUT std_logic_VECTOR(9 downto 0);

full : OUT std_logic;

empty : OUT std_logic;

rd_ack : OUT std_logic;

wr_ack : OUT std_logic);

END afifo_maxsdi;


ARCHITECTURE afifo_maxsdi_a OF afifo_maxsdi IS
component wrapped_afifo_maxsdi

port (


din: IN std_logic_VECTOR(9 downto 0);

wr_en: IN std_logic;

wr_clk: IN std_logic;

rd_en: IN std_logic;

rd_clk: IN std_logic;

ainit: IN std_logic;

dout: OUT std_logic_VECTOR(9 downto 0);

full: OUT std_logic;

empty: OUT std_logic;

rd_ack: OUT std_logic;

wr_ack: OUT std_logic);

end component;


-- Configuration specification

for all : wrapped_afifo_maxsdi use entity XilinxCoreLib.async_fifo_v4_0(behavioral)

generic map(

c_use_blockmem => 1,

c_rd_count_width => 2,

c_has_wr_ack => 1,

c_has_almost_full => 0,

c_has_wr_err => 0,

c_wr_err_low => 0,

c_wr_ack_low => 0,

c_data_width => 10,

c_enable_rlocs => 0,

c_rd_err_low => 0,

c_wr_count_width => 2,

c_rd_ack_low => 0,

c_has_rd_count => 0,

c_has_almost_empty => 0,

c_has_rd_ack => 1,

c_has_wr_count => 0,

c_fifo_depth => 1023,

c_has_rd_err => 0);

BEGIN
U0 : wrapped_afifo_maxsdi

port map (

din => din,

wr_en => wr_en,

wr_clk => wr_clk,

rd_en => rd_en,

rd_clk => rd_clk,

ainit => ainit,

dout => dout,

full => full,

empty => empty,

rd_ack => rd_ack,

wr_ack => wr_ack);

END afifo_maxsdi_a;
-- synopsys translate_on

-------------------------------------------

-- GIANT Project

-- NTUA


-------------------------------------------

--------------------------------------------------------------------

-- Design Unit Name : Timer_Service

-- Purpose : This entity is responsible to service the AllocID that previously

-- has been detected by "timer_inspection" entity

--


-- File Name : gbw_ts.vhd

--------------------------------------------------------------------

-- Description

-- For every AllocId stored in the timers_fifo, which indicates that guaranteed bandwidth and polling has to be assigned,

-- it accesses the BAP and the Request Matrix in order to calculate the Allocation bytes. It also obtains

-- the residence ONU ID, to check with ONU service whether a PLOAM has to be assigned and to provide it to the

-- asp to check whether a PLOu has to be inserted between the allocations. When allocation bytes are not zero,

-- and T-CONT 2, 3 or 4 is being serviced, the update request matrix is triggered to update the pending

-- requests.

--------------------------------------------------------------------------

-- Design notes

-- 1. The access of BAP and REQUEST MATRIX are made in parallel

-- 2. The ts entity makes an immediate request to ONU_service so as the asp entity be informed

-- about the PLOAM and PLSu flags

--------------------------------------------------------------------

-- Design improvement

-- The calculation of the Allocation bytes requires a huge combinatorial circuit. Hence, it the design

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